jotego / jt51 Goto Github PK
View Code? Open in Web Editor NEWYM2151 clone in verilog. FPGA proven.
License: GNU General Public License v3.0
YM2151 clone in verilog. FPGA proven.
License: GNU General Public License v3.0
The drums sound too low, they should sound much louder.
The envelope seems wrong and it gets fixed if pre_rate_III is not scaled:
case( ks_III )
2'd3: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 2'b0, keycode_III };
2'd2: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 3'b0, keycode_III[4:1] };
2'd1: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 4'b0, keycode_III[4:2] };
2'd0: pre_rate_III = { 1'b0, cfg_III, 1'b0 } + { 5'b0, keycode_III[4:3] };
endcase
If keycode_III is made 0, the drum can be heard. The keycode seems to trigger a fast attack rate (1F) although the channel (ch 7, op 3) should have keycode = 0.
The problem can be heard in commit e3907d7 by running
go -f willow.vgm -time 2200 -w0 1600
The following JTT file yields no wave output:
$020,C7
$028,4A
$040,01
$060,00
$080,1F
$0A0,00
$0E0,FF
$008,08
$028,4A # This is a duplicate (i.e. redundant) write
wait 1000
However, if I remove the last (duplicate) write to @028.4A
(which could be any other write), then the expected waveform is generated (440 Hz sine wave @ -6 dB).
Likewise, if I insert a "wait 5" to the following:
$020,C7
$028,4A
$040,01
$060,00
$080,1F
$0A0,00
$0E0,FF
wait 5
$008,08
$028,4A # This is a duplicate (i.e. redundant) write
wait 1000
then again the correct waveform is generated.
It appears (by viewing the signal waveform in the generated FST file) that the signal u_mmr.u_reg.u_kon.up_keyon
indeed goes to 1 for some time, but then goes back to 0 just before u_mmr.u_reg.u_kon.cur_op_hot
achieves the value 1.
$./jt51_singlefile.sh
jt51_phinc_rom.v
jt51_exprom.v
jt51_phrom.v
jt51_lin2exp.v
jt51_exp2lin.v
jt51_mmr.v
jt51_reg.v
jt51.v
jt51_acc.v
jt51_timers.v
jt51_eg.v
jt51_op.v
jt51_sh.v
jt51_pg.v
jt51_lfo.v
Cannot find file /home/pi/jt51/hdl/jt51_lfo_lfsr.v
Hi, testing your code in the MSX1FPGA with Double Dragon VGM, there are some troubles with initial state of some registers. If they are initialized all with 0xFF the song works.
I made a change in the jt51_reg.v for this:
--- jt51\jt51_reg.v 2017-12-07 10:17:14.000000000 -0300
+++ jt51\jt51_reg.v.orig 2018-09-27 10:44:35.706000000 -0300
@@ -218,15 +218,6 @@
localparam opreg_w = 42;
reg [opreg_w-1:0] reg_op[31:0];
reg [opreg_w-1:0] reg_out;
-integer i;
-
-initial
-begin
- for (i=0; i<32; i=i+1)
- begin
- reg_op[i] = ~0;
- end
-end
assign { dt1_II, mul_VI, tl_VII, ks_III, amsen_VII,
dt2_I, d1l_I, arate_II, rate1_II, rate2_II, rrate_II } = reg_out;
Note that this can never be heard in real life.
See the section "What is wrong with GPL for FPGA design?"
https://ohwr.org/project/cernohl/wikis/faq
Probably using one of the reciprocal CERN open hardware
licenses would be equivalent to the GPL but much easier to interpret/use.
This is useful for replacing an original chip on a board. Not sure if it is ever needed for FPGA arcade cores.
In the file "ym2151_app_notes.pdf" on page 7 it is stated that setting the Key Code register to 0x4A generates a frequency of 440 Hz. This is in agreement with Figure 2.4 on page 18, where a maximal output frequency of 4186 Hz is mentioned.
However, the implementation in this repository instead generates 220 Hz with a Key Code of 0x4A. And a maximal frequency of 2093 Hz with a Key Code of 0x7E. So it appears the frequencies in this implementation are too low by a factor of 2 compared to the documentation.
I don't have access to a real YM2151 chip, so I don't know whether this is an error in the implementation or in the documentation. Furthermore, the YM2151 emulator in https://github.com/mamedev/mame appears to agree with this implementation.
It could also be an error in the test stimuli I generate, however I'm pretty sure I've done it correctly:
Is there something I have misunderstood? Is there an error in the chip documentation?
Checking out the repo with git clone --recurse-submodules shows the following error messages in the shell:
Submodule path 'modules/jt51': checked out '48c12e2fcb2e03163423ca21cead995f41dd5978'
Submodule 'mc6809' ([email protected]:cavnex/mc6809.git) registered for path 'mc6809'
Cloning into 'mc6809'...
Warning: Permanently added the RSA host key for IP address '140.82.118.3' to the list of known hosts.
Permission denied (publickey).
fatal: Could not read from remote repository.
Please make sure you have the correct access rights
and the repository exists.
Clone of '[email protected]:cavnex/mc6809.git' into submodule path 'mc6809' failed
Must change to keyon implementation like that of JT12
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