Comments (2)
This is because the verw
and verr
are not supported. If we add them, it should fix this issue.
from triton.
Commit 20393f5 add supports for verr
and verw
. It should fix this issue.
from triton.
Related Issues (20)
- Taint resulting from a dereference HOT 2
- Taint propagation on conditional jumps HOT 1
- Once contain “inc edi” or “dec edi”,TritonContext.disassembly(block, start) generate TypeError: x8664Cpu::disassembly(): Failed to disassemble the given code. HOT 3
- Will a new official version be released soon? HOT 3
- Problem with getWrittenRegisters() in aarch64
- ARM32 - `ADR` Instruction incorrect behaviour HOT 3
- Why is this POC yielding these results? HOT 2
- Failed to build with the library HOT 5
- Clarification regarding MEMORY_ARRAY mode HOT 7
- symbolizeRegister result is different with setConcreteRegisterValue result ?
- How to determine if a concrete register value is known? HOT 2
- fails to build against LLVM-18
- [OSX ERROR] SystemError: initialization of triton did not return an extension module HOT 7
- lea semantic bugg ?
- LDRSW instruction error ?
- Incorrectly handled x86 instruction, rcl memory, immediate HOT 2
- Trying to collect symbolic address from MemoryAccess HOT 2
- Add Dissasembly callbacks? HOT 2
- Is it possible to symbolize arbitrary memory access before the actual processing? HOT 1
- Building errors on python3.12
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