Implementation of a simple RISC style processor for on an Altera DE0 Cyclone III board. Created using VHDL and Altera Quartus II. Project created for course project in ELEC 374 Computer Architecture course at Queen's University.

These instructions will get you a copy of the project up and running on your local machine for development and testing purposes. See deployment for notes on how to deploy the project on a live system.

What things you need to install the software and how to install them

Altera Quartus II
Model Sim Altera Quartus Addon
Altera DE0 board (not required for only simulation activities)

1. Start Altera Quartus II
2. Open SRC_CPU.qpf project file
3. Investigate VHDL contents for each component of the CPU.
   1. Example, workingBooth.vhd implements the Booth's multiplication algorithm.
   2. Another example, datapath.vhd combines all components required for the CPU's datapath.
4. Use ModelSim to simulate various CPU functions. Image below shows a shift right register simulation (Other screenshots can be found in Simulation_Pictures directory).

• Madeline Van Der Paelt
• Maytha Nassor
• Johan Cornelissen

• Prof. Ahmad Afsahi, Instructor of ELEC 374 Computer Architecture during Winter 2016.