50.002 Computation Structures @ SUTD

1D project

• Construction of a 1-bit full adder with an FPGA tester (/1-bit-full-adder-FPGA/)

2D project

• Optimization of a 32-bit adder (/32-bit-adder-2D/)

3 variants with different trade-offs were tested: the Kogge-Stone (large area, high speed, minimal fanout), Sklansky (divide and conquer, high fanout), and Brent-Kung (lowest area, high logic depth, minimal fanout) architectures.

Beta RISC Architecture

• Implementation of MIT's Beta RISC architecture (/beta/): program counter logic, control logic, and register file implementation.