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SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

License: Apache License 2.0

ANTLR 4.05% C++ 58.02% SystemVerilog 19.82% Tcl 1.82% Python 1.66% C 0.07% Makefile 0.13% Forth 0.01% Verilog 12.46% V 0.04% CMake 0.94% Slash 0.72% Shell 0.25% SWIG 0.01% Nix 0.02%

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