from myhdl import always_seq, instance, StopSimulation
    from uhdl import Clock, Reset, Sig, randbits, HW, run

    def inc(clk, rst, en, count):
        @always_seq(clk.posedge, rst)
        def logic():
            if en:
                count.next = count + 1
        return logic

    #Simulation(test_inc()).run()
    @run
    def test_inc(backend):
        clk = Clock()
        rst = Reset(async=False)
        en = Sig(False)
        count = Sig(8) #Signal(intbv()[8:])
        top = HW(inc, clk, rst, en, count)
        dut = top.sim(backend=backend)

        @instance
        def stim():
            for i in range(20):
                en.next = randbits(1)
            raise StopSimulation

        @instance
        def mon():
            while True:
                yield clk.posedge
                yield delay(1)
                print rst, en, count

        #If the function was not decorated with @run, 
        #run(clk.gen(), rst.pulse(), dut, stim, mon) would do the trick.
        return clk.gen(), rst.pulse(5), dut, stim, mon

    #run with myhdl
    test_inc()
    #run with icarus
    test_inc('icarus')
    #run with modelsim
    test_inc('modelsim')