Comments (7)
Hi, do you have CS_N set to GND? And SCLK is without parasitic peaks, which could cause poor edge detection? You can try a Signal Tap (part of Quartus) to debug the signals inside the FPGA.
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Yes, different voltage level could be a problem. Your test check only one direction (FPGA -> Arduino), right? But problem can be on oppostite direction. You can try simple voltage divider from resistors for voltage conversion from 5V to 3.3V (Arduino -> FPGA).
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Also try SignalTap tool, then we will see the signals inside the FPGA and what is wrong.
Some tutorials about SignalTap:
http://pages.hmc.edu/harris/class/e155/SignalTap.pdf
http://scale.engin.brown.edu/classes/EN164S17/SignalTap.pdf
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Please send me some screenshoots from SignalTap with the waveforms of all i/o SPI Slave ports and the waveforms of these internal signals: spi_clk_redge_en, spi_clk_fedge_en, bit_cnt_max, load_data_en, slave_ready, shreg_busy, rx_data_vld.
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Related Issues (8)
- Support for different transfer size HOT 2
- spi slave miso test HOT 1
- Maximum SCLK frequency on SPI SLAVE module HOT 2
- Possible Meta-Stability Issue in Slave Module HOT 1
- A question about sclk edge HOT 4
- Question: spi slave sim with just master => slave mosi data transfer HOT 4
- spi slave in hw => dout_vld no creating '1' value HOT 4
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