Comments (1)
jakubcabal
commented on August 16, 2024
Hi,
right after the reset you probably have bad data on signal DIN, even though signal DIN_VLD is set to '1'. You must have the DIN_VLD signal active only when you have the correct data on the DIN signal. Data from the DIN signal is accepted only in the clock cycle when DIN_VLD and DIN_RDY are active at the same time.
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