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test

this is a test issue

#14 is a duplicate

access-order of fields is not documented correctly -- SIMICS-19021

The documentation for read_register states that fields are read lsb first.
The documentation for write_register states that fields are written msb first.
The actual implementation is:

For read:

  1. fields without read-template are retrieved all at once
  2. fields with read-template are read lsb first

For write:

  1. fields with write-template are written lsb first
  2. fields without write-template are written all at once

Either documentation or implementation needs to be updated.

ecarsten added a comment - 10/Mar/22 2:01 PM:
Doc should be updated so read and write use the same direction. Implementation should be updated accordingly (looks easy).

ecarsten added a comment - 11/Mar/22 7:54 PM:
The documentation for read_register states that fields are read lsb first.

I would interpret the documentation for read as "msb first":

The implementation invokes the `read_field` method of
all sub-fields at least partially covered by `enabled_bytes`, in order
from most to least significant bit.  

In any case, this is inconsistent with the implementation, which accesses LSB first. Test of current behaviour:

--- a/test/1.4/lib/T_field.dml
+++ b/test/1.4/lib/T_field.dml
@@ -37,4 +37,14 @@ bank b {
     register r4 size 4 @ 12 {
         field f @ [31:0] is use_get_val;
     }
+
+    register r5 size 4 @ 16 {
+        saved uint64 written;
+        field a[i < 4] @ [i * 8 + 7 : i * 8] is write {
+            method write(uint64 val) {
+                written <<= 8;
+                written[7:0] = val;
+            }
+        }
+    }
 }
diff --git a/test/1.4/lib/T_field.py b/test/1.4/lib/T_field.py
index 9496f1d9..3233107e 100644
--- a/test/1.4/lib/T_field.py
+++ b/test/1.4/lib/T_field.py
@@ -7,3 +7,7 @@ for name in ['r1', 'r2', 'r3', 'r4']:
     setattr(obj, 'b_' + name, 4)
     # set adds 1, get adds 2
     stest.expect_equal(getattr(obj, 'b_' + name), 7)
+
+dev_util.Register_LE(obj.bank.b, 16).write(0xaabbccdd)
+# lsb written first
+stest.expect_equal(obj.bank.b.r5_written, 0xddccbbaa)

The 1.2 behaviour is to access MSB first, as documented, so either we have to switch existing 1.4 devs from LSB-first to MSB-first, or we have to migrate every remaining 1.2 dev from MSB-first to LSB-first while migrating to 1.4 (possibly with extra pain from supporting both orders in parallel during a migration window). Both seem like similar amounts of work. Any opinions on which one is preferable?

I recall from ancient times that the 1.2 order (MSB first) happened to be practical more often than it was impractical. OTOH, most regs use little-endian byte order which makes "LSB first" feel more natural (it means that the field with lowest address is written first, if different fields cover different bytes).

This repository should provide a link to DML 1.4 reference manual and style guide

I've noticed its not really easy to access this manual by searching the web. I get some links to 1.2 reference manual, but given DMLC here does support 1.4 and the source is public, the language reference manual for 1.4 and the style guide should be accessible as well.

I suggest to find some way to distribute the manual and link it here in the repo, maybe in the README

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