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embedded-stereo-vision

High performance embedded systems for stereoscopic vision

endpointai

ese-566-parking-spot-finder-soc-design

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

espresso-logic-minimizer

A Node.js bridge to the Espresso heuristic logic minimizer original C code

ester

Ester 3D Laser Printer

event-based_vision_resources

examples

fabulous

Fabric generator and CAD tools

feelsketch

Automatically exported from code.google.com/p/feelsketch

femu

FEMU: NVMe SSD Emulator (FAST'18)

firesim-nvdla

FireSim-NVDLA: NVIDIA Deep Learning Accelerator (NVDLA) Integrated with RISC-V Rocket Chip SoC Running on the Amazon FPGA Cloud

flamegraph

Stack trace visualizer

flowblaze

FlowBlaze: Stateful Packet Processing in Hardware

fpga-sdcard-reader

FPGA-based SDcard Reader via SD bus.

fpga-stereo-camera-basys3

Integration of two camera modules to Basys 3 FPGA

fpga-vision

Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. Real hardware is available as a remote lab.

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

fpga-zynqnet

FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS

fpga_depthmap

Using stereo vision to identify the obstacles by processing images on a FPGA

fpga_image_processing

IP operations in verilog (simulation and implementation on ice40)

fpga_threelevelstorage

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

fpga_vr_blockmatching

fpgadesignelements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.

free-tpu

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

freedom

freedom-1

riscv unofficial

gcw0_vpu_poc

Proof of concept for using the Ingenic JZ4770 vpu core on GCW Zero

gem5

This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews should be submitted to https://gem5-review.googlesource.com/. The mirrors are synchronized every 15 minutes.

gem5.tnt

gem5 Tips & Tricks