The CV32E40P processor core, developed by the OpenHW Group, showcases notable advancements in the RISC-V architecture. Extending the Instruction Set Architecture (ISA) of CV32E40P, the design incorporates a range of supplementary instructions such as hardware loops, post-increment load and store instructions, and additional ALU instructions, which extends the standard RISC-V ISA.
This project involves the Layered Testbench-based Verification of the modules of the Processor.
Documentation of the Processor has been added to the repository along with a detailed report of the project.