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Hi, I'm Abhishek πŸ‘‹πŸΎ

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  • πŸ”­ I’m currently working on designing processor cores and accelerator designs
  • 🌱 I’m currently learning FPGAs, SystemVerilog, and Computer Architecture
  • πŸ‘― I’m looking to collaborate on open-source hardware projects and accelerator designs
  • πŸ€” I’m looking for help with designing concepts and Computer Architecture Projects
  • πŸ’¬ Ask me anything related to Hardware, VLSI Design, Computer Architecture, Life, and Society in general.
  • πŸ“« I would love to read your emails, email me at [email protected]
  • πŸ˜„ Pronouns: He/Him/His
  • ⚑ Fun fact: DIGITAL ELECTRONIC SYSTEMS have NO RELEVANCE in real-world if they don’t have ANALOG CIRCUITS

I'm a final year undergraduate student at Indian Institute of Information Technology Dharwad, Karnataka, India pursuing my BTech in Electronics and Communication Engineering. In my undergrad so far I have worked with FPGAs, Microcontrollers, and Circuit Designs. I'm also an undergraduate researcher who had worked under the guidance of Dr. Prabhu Prasad B M and Dr. Jagadish D N at the Department of CSE and ECE. I was also a research intern at Defence Research and Development Organisation, Delhi, India in the summer of 2021.
I am also a huge supporter of Open-Source Hardware and EDA Tools.

I'm always open to Research/Internship Opportunities in :

  • Computer Architecture
  • RTL Design, Verification and Synthesis
  • FPGA prototyping
  • Software/Hardware Co-Design
  • Digital Integrated Circuit Design
  • RISC V and other Processor Design
  • HW Accelerator Design for different applications


Connect with me :

Abhishek's LinkedIn Abhishek's Gmail ID Abhishek's GitHub Abhishek's Twitter

Abhishek Singh Kushwaha's Projects

oh icon oh

Verilog library for ASIC and FPGA designers

resume.md icon resume.md

Write your resume in Markdown, style it with CSS, output to HTML and PDF

rtl_notes icon rtl_notes

Notes I made on RTL design and verification. Currently has verilog, system verilog and formal verification notes

tnoc icon tnoc

Network on Chip Implementation written in SytemVerilog

vsd_pll icon vsd_pll

8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.

vsd_rtl icon vsd_rtl

This repo contains the detail of labs and designs implemented and simulated during the 5 day workshop at VSD

zoom-class-work icon zoom-class-work

I have submitted the class work given by our professor on Zoom class.

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