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linux-mainline-mediatek-mt81xx-kernel's Introduction
# directories: # - /compile/doc/stable-mt - the files in this dir # - /compile/source/linux-stable-mt7 - the kernel sources checked out from gitrepo # - /compile/result/stable-mt - the resulting kernel, modules etc. tar.gz files # - /compile/doc/kernel-config-options - https://github.com/hexdump0815/kernel-config-options # name: stb-mt7 - chromebook mediatek mt817x # it looks like for newer kernel versions like v6.5 the following packages have to be # installed in order to get the tool compiled well: libelf-dev python3-dev libtraceevent-dev cd /compile/source/linux-stable-mt7 # patches for mt8173/oak for i in /compile/doc/stable-mt/misc.cbm/patches/v6.6/mt8173*.patch; do echo === $i patch -p1 < $i done # patches for mt81xx for i in /compile/doc/stable-mt/misc.cbm/patches/v6.6/mt81xx*.patch; do echo === $i patch -p1 < $i done export ARCH=arm64 scripts/kconfig/merge_config.sh -m arch/arm64/configs/defconfig /compile/doc/kernel-config-options/chromebooks-aarch64.cfg /compile/doc/kernel-config-options/mediatek.cfg /compile/doc/kernel-config-options/docker-options.cfg /compile/doc/kernel-config-options/options-to-remove-generic.cfg /compile/doc/stable-mt/misc.cbm/options/options-to-remove-special.cfg /compile/doc/kernel-config-options/additional-options-generic.cfg /compile/doc/kernel-config-options/additional-options-aarch64.cfg /compile/doc/stable-mt/misc.cbm/options/additional-options-special.cfg ( cd /compile/doc/kernel-config-options ; git rev-parse --verify HEAD ) > /compile/doc/stable-mt/misc.cbm/options/kernel-config-options.version make olddefconfig ./scripts/config --set-str CONFIG_LOCALVERSION "-stb-mt7" make -j 4 Image dtbs modules cd tools/perf # this is to avoid compile errors export NO_JEVENTS=1 make cd ../power/cpupower make cd ../../.. export kver=`make kernelrelease` echo ${kver} # remove debug info if there and not wanted #find . -type f -name '*.ko' | sudo xargs -n 1 objcopy --strip-unneeded make modules_install mkdir -p /lib/modules/${kver}/tools cp -v tools/perf/perf /lib/modules/${kver}/tools cp -v tools/power/cpupower/cpupower /lib/modules/${kver}/tools cp -v tools/power/cpupower/libcpupower.so.0.0.1 /lib/modules/${kver}/tools/libcpupower.so.0 # make headers_install INSTALL_HDR_PATH=/usr cp -v .config /boot/config-${kver} cp -v arch/arm64/boot/Image /boot/Image-${kver} mkdir -p /boot/dtb-${kver} cp -v arch/arm64/boot/dts/mediatek/mt8173*.dtb /boot/dtb-${kver} cp -v System.map /boot/System.map-${kver} # start chromebook special - required: apt-get install liblz4-tool vboot-kernel-utils cp arch/arm64/boot/Image Image lz4 -f Image Image.lz4 dd if=/dev/zero of=bootloader.bin bs=512 count=1 cp /compile/doc/stable-mt/misc.cbm/misc/cmdline cmdline ls arch/arm64/boot/dts/mediatek/mt8173-*.dtb | xargs printf " -b %s" | xargs mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lz4 -a 0 -d Image.lz4 kernel.itb vbutil_kernel --pack vmlinux.kpart --keyblock /usr/share/vboot/devkeys/kernel.keyblock --signprivate /usr/share/vboot/devkeys/kernel_data_key.vbprivk --version 1 --config cmdline --bootloader bootloader.bin --vmlinuz kernel.itb --arch arm cp -v vmlinux.kpart /boot/vmlinux.kpart-${kver} rm -f Image Image.lz4 cmdline bootloader.bin kernel.itb vmlinux.kpart # end chromebook special cd /boot update-initramfs -c -k ${kver} #mkimage -A arm64 -O linux -T ramdisk -a 0x0 -e 0x0 -n initrd.img-${kver} -d initrd.img-${kver} uInitrd-${kver} tar cvzf /compile/source/linux-stable-mt7/${kver}.tar.gz /boot/Image-${kver} /boot/System.map-${kver} /boot/config-${kver} /boot/dtb-${kver} /boot/initrd.img-${kver} /boot/vmlinux.kpart-${kver} /lib/modules/${kver} cp -v /compile/doc/stable-mt/config.mt7 /compile/doc/stable-mt/config.mt7.old cp -v /compile/source/linux-stable-mt7/.config /compile/doc/stable-mt/config.mt7 cp -v /compile/source/linux-stable-mt7/.config /compile/doc/stable-mt/config.mt7-${kver} cp -v /compile/source/linux-stable-mt7/*.tar.gz /compile/result/stable-mt
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linux-mainline-mediatek-mt81xx-kernel's Issues
want to find a way to boot this on a mt8183 android tablet
tablet is asus adol pad P030 (aka apad 10 pro), it have a MT8788 BSP Android 10 with kernel 4.14.141+(mp1V9110)
I can attach to UART port, and found it using LK(little kernel) as old MTK SoC did.
I also found a guide , but failed when trying.
https://github.com/freedomtan/X20-96-board/wiki/booting-mainline-kernel
It can boot into fastboot but failed when booting mainlineboot.img
the screen driver is hx8279_sl101pm32d1720_wuxga_b06 , touch controler is silead gsl3692.
DeviceTree from fs :
asus_apad10pro_p030.dts
/dts-v1/;
/ {
compatible = "mediatek,mt6771";
interrupt-parent = <0x01>;
#size-cells = <0x02>;
model = "MT6771V/WM";
#address-cells = <0x02>;
kp@10010000 {
mediatek,kpd-hw-recovery-key = <0x11>;
mediatek,kpd-pwrkey-eint-gpio = <0x00>;
mediatek,kpd-hw-pwrkey = <0x08>;
mediatek,kpd-hw-rstkey = <0x11>;
mediatek,kpd-hw-init-map = <0x72 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
phandle = <0x28>;
reg = <0x00 0x10010000 0x00 0x1000>;
mediatek,kpd-hw-dl-key0 = <0x11>;
mediatek,kpd-hw-map-num = <0x48>;
status = "okay";
mediatek,kpd-hw-factory-key = <0x00>;
mediatek,kpd-hw-dl-key2 = <0x08>;
compatible = "mediatek,kp";
mediatek,kpd-sw-pwrkey = <0x74>;
mediatek,kpd-sw-rstkey = <0x73>;
mediatek,kpd-pwkey-gpio-din = <0x00>;
mediatek,kpd-key-debounce = <0x400>;
interrupts = <0x00 0xba 0x02>;
mediatek,kpd-use-extend-type = <0x00>;
mediatek,kpd-hw-dl-key1 = <0x00>;
};
md2g_confg@82c00000 {
reg = <0x00 0x82c00000 0x00 0x1000>;
compatible = "mediatek,md2g_confg";
};
scp_cfgreg@105c0000 {
reg = <0x00 0x105c0000 0x00 0x1000>;
compatible = "mediatek,scp_cfgreg";
};
md_lite_gpt@80170000 {
reg = <0x00 0x80170000 0x00 0x1000>;
compatible = "mediatek,md_lite_gpt";
};
mipi_tx0@11e50000 {
reg = <0x00 0x11e50000 0x00 0x1000>;
compatible = "mediatek,mipi_tx0";
};
rake_dc@87430000 {
reg = <0x00 0x87430000 0x00 0x1000>;
compatible = "mediatek,rake_dc";
};
bc@876c0000 {
reg = <0x00 0x876c0000 0x00 0x1000>;
compatible = "mediatek,bc";
};
l2calmac@85098000 {
reg = <0x00 0x85098000 0x00 0x1000>;
compatible = "mediatek,l2calmac";
};
i2c@11009000 {
phandle = <0x58>;
mediatek,use-open-drain;
reg = <0x00 0x11009000 0x00 0x1000 0x00 0x11000280 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
ccu-ch-offset = <0x200>;
clocks = <0x15 0x0d 0x15 0x2b 0x15 0x4a>;
interrupts = <0x00 0x53 0x08>;
id = <0x02>;
ch_offset_default = <0x100>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
clock-div = <0x05>;
camera_sub@10 {
phandle = <0x12b>;
reg = <0x10>;
status = "okay";
compatible = "mediatek,camera_sub";
};
};
apirq@1000b000 {
phandle = <0x27>;
reg = <0x00 0x1000b000 0x00 0x1000>;
compatible = "mediatek,apirq";
interrupts = <0x00 0xb1 0x04>;
};
bpi_2g@83080000 {
reg = <0x00 0x83080000 0x00 0x1000>;
compatible = "mediatek,bpi_2g";
};
smi_common_ao@10211000 {
reg = <0x00 0x10211000 0x00 0x1000>;
compatible = "mediatek,smi_common_ao";
};
scpsys@10001000 {
phandle = <0x2e>;
reg = <0x00 0x10001000 0x00 0x1000 0x00 0x10006000 0x00 0x1000 0x00 0x1020e000 0x00 0x1000 0x00 0x10000000 0x00 0x1000 0x00 0x1a001000 0x00 0x1000 0x00 0x14019000 0x00 0x1000>;
compatible = "mediatek,scpsys";
#clock-cells = <0x01>;
};
mdp_rdma0@14001000 {
phandle = <0x31>;
reg = <0x00 0x14001000 0x00 0x1000>;
compatible = "mediatek,mdp_rdma0";
clocks = <0x2f 0x0d>;
interrupts = <0x00 0xda 0x08>;
clock-names = "MDP_RDMA0";
};
rxsrp@87800000 {
reg = <0x00 0x87800000 0x00 0x1000>;
compatible = "mediatek,rxsrp";
};
hsce_dc@87420000 {
reg = <0x00 0x87420000 0x00 0x1000>;
compatible = "mediatek,hsce_dc";
};
mipi_rx_ana_csi0a@11c80000 {
reg = <0x00 0x11c80000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi0a";
};
rt5081_pd_eint {
phandle = <0xbc>;
};
m4u@10205000 {
reg = <0x00 0x10205000 0x00 0x1000>;
compatible = "mediatek,m4u";
interrupts = <0x00 0xa6 0x08>;
cell-index = <0x00>;
};
infra_md_cfg@1021d000 {
reg = <0x00 0x1021d000 0x00 0x1000>;
compatible = "mediatek,infra_md_cfg";
};
h_rxbrp@87650000 {
reg = <0x00 0x87650000 0x00 0x1000>;
compatible = "mediatek,h_rxbrp";
};
spi2@11012000 {
mediatek,pad-select = <0x00>;
phandle = <0x9a>;
reg = <0x00 0x11012000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x3c>;
interrupts = <0x00 0x81 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
vdec_pp@16025000 {
reg = <0x00 0x16025000 0x00 0x1000>;
compatible = "mediatek,vdec_pp";
};
mfgcfg@13000000 {
phandle = <0x46>;
reg = <0x00 0x13000000 0x00 0x1000 0x00 0x10001000 0x00 0x1000 0x00 0x10006000 0x00 0x1000 0x00 0x1020e000 0x00 0x1000 0x00 0xd000000 0x00 0xf0000>;
compatible = "mediatek,mfgcfg\0syscon";
#clock-cells = <0x01>;
};
scp_uart1@105ce000 {
reg = <0x00 0x105ce000 0x00 0x1000>;
compatible = "mediatek,scp_uart1";
};
c2ksys@38000000 {
reg = <0x00 0x38000000 0x00 0x1000>;
compatible = "mediatek,c2ksys";
};
mdpar_dbgmon@800b0000 {
reg = <0x00 0x800b0000 0x00 0x1000>;
compatible = "mediatek,mdpar_dbgmon";
};
dynamic_options {
phandle = <0xb2>;
compatible = "mediatek,dynamic_options";
};
disp_ovl0@14008000 {
reg = <0x00 0x14008000 0x00 0x1000>;
compatible = "mediatek,disp_ovl0";
interrupts = <0x00 0xe1 0x08>;
};
smi_larb5@15021000 {
reg = <0x00 0x15021000 0x00 0x1000>;
compatible = "mediatek,smi_larb5\0mediatek,smi_larb";
mediatek,smi-id = <0x05>;
clocks = <0x2e 0x05 0x2f 0x08 0x49 0x0a>;
interrupts = <0x00 0x10b 0x08>;
clock-names = "mtcmos-isp\0gals-img2mm\0img-larb5";
};
l2dlsecctl@850b8000 {
reg = <0x00 0x850b8000 0x00 0x1000>;
compatible = "mediatek,l2dlsecctl";
};
battery {
battery0_profile_t2 = <0x00 0xa963 0x00 0x30b 0xa884 0x4a6 0x617 0xa7db 0x4ad 0x922 0xa74d 0x4b0 0xc2e 0xa6c7 0x4b0 0xf39 0xa647 0x4b4 0x1244 0xa5cb 0x4b0 0x1550 0xa551 0x4b1 0x185b 0xa4db 0x4b5 0x1b67 0xa468 0x4b5 0x1e72 0xa3f6 0x4ba 0x217d 0xa386 0x4bc 0x2489 0xa316 0x4bd 0x2794 0xa2a8 0x4be 0x2aa0 0xa23a 0x4ba 0x2dab 0xa1cd 0x4c0 0x30b6 0xa15f 0x4c3 0x33c2 0xa0f1 0x4c0 0x36cd 0xa085 0x4c7 0x39d8 0xa01e 0x4ce 0x3ce4 0x9fc5 0x4d4 0x3fef 0x9f82 0x4de 0x42fb 0x9f3a 0x4a1 0x4606 0x9ece 0x35f 0x4911 0x9e62 0x36d 0x4c1d 0x9dbb 0x35d 0x4f28 0x9d0a 0x357 0x5234 0x9c76 0x358 0x553f 0x9c03 0x35b 0x584a 0x9bb0 0x362 0x5b56 0x9b74 0x36a 0x5e61 0x9b48 0x375 0x616d 0x9b1f 0x37e 0x6478 0x9ae2 0x37c 0x6783 0x9a96 0x376 0x6a8f 0x9a46 0x375 0x6d9a 0x99f2 0x373 0x70a6 0x999a 0x36f 0x73b1 0x9939 0x365 0x76bc 0x98d4 0x359 0x79c8 0x986e 0x34c 0x7cd3 0x9809 0x33e 0x7fdf 0x97ab 0x334 0x82ea 0x9758 0x32c 0x85f5 0x970c 0x326 0x8901 0x96c7 0x323 0x8c0c 0x9688 0x321 0x8f18 0x964e 0x321 0x9223 0x9618 0x321 0x952e 0x95e5 0x323 0x983a 0x95b5 0x324 0x9b45 0x9589 0x327 0x9e50 0x955f 0x32a 0xa15c 0x9536 0x32c 0xa467 0x950f 0x32f 0xa773 0x94e8 0x331 0xaa7e 0x94c5 0x335 0xad89 0x94a3 0x338 0xb095 0x9481 0x33a 0xb3a0 0x9463 0x33d 0xb6ac 0x9446 0x340 0xb9b7 0x942a 0x341 0xbcc2 0x940e 0x343 0xbfce 0x93f4 0x345 0xc2d9 0x93da 0x347 0xc5e5 0x93c0 0x347 0xc8f0 0x93a5 0x347 0xcbfb 0x9389 0x346 0xcf07 0x936c 0x344 0xd212 0x934e 0x342 0xd51e 0x932d 0x340 0xd829 0x930a 0x33e 0xdb34 0x92e6 0x33b 0xde40 0x92ee 0x35a 0xe14b 0x92e4 0x429 0xe457 0x92c6 0x4d6 0xe762 0x92a7 0x505 0xea6d 0x9285 0x516 0xed79 0x925f 0x525 0xf084 0x9230 0x52b 0xf390 0x91fa 0x53a 0xf69b 0x91c2 0x545 0xf9a6 0x918d 0x54e 0xfcb2 0x9153 0x564 0xffbd 0x910a 0x572 0x102c8 0x90c3 0x57e 0x105d4 0x9096 0x59b 0x108df 0x907e 0x5c0 0x10beb 0x906e 0x5ec 0x10ef6 0x905a 0x627 0x11201 0x903a 0x671 0x1150d 0x8fea 0x6bd 0x11818 0x8f02 0x6e0 0x11b24 0x8d5c 0x716 0x11e2f 0x8b23 0x78e 0x1213a 0x880c 0x84c 0x12446 0x8367 0x915 0x12751 0x7d81 0x5a2 0x12a5d 0x7d3f 0x576 0x12d68 0x7d3f 0x576>;
KEEP_100_PERCENT = <0x02>;
Q_MAX_SYS_VOLTAGE_BAT1 = <0xd48>;
g_FG_PSEUDO100_T2 = <0x64>;
EMBEDDED_SEL = <0x00>;
SHUTDOWN_GAUGE0_VOLTAGE = <0x84d0>;
battery0_profile_t4_num = <0x64>;
battery0_profile_t4 = <0x00 0xa881 0x00 0x30b 0xa741 0xecd 0x617 0xa674 0xef5 0x922 0xa5d0 0xefc 0xc2e 0xa540 0xefb 0xf39 0xa4bc 0xef7 0x1244 0xa444 0xef2 0x1550 0xa3cd 0xeec 0x185b 0xa359 0xee6 0x1b67 0xa2e8 0xedf 0x1e72 0xa276 0xed7 0x217d 0xa204 0xecf 0x2489 0xa195 0xeca 0x2794 0xa126 0xea6 0x2aa0 0xa0ba 0xeb4 0x2dab 0x9bfa 0xbc9 0x30b6 0x9ac9 0xe1e 0x33c2 0x9a35 0xe9e 0x36cd 0x99b3 0xe83 0x39d8 0x9959 0xe76 0x3ce4 0x990c 0xe6a 0x3fef 0x98c3 0xe5f 0x42fb 0x987b 0xe54 0x4606 0x982f 0xe45 0x4911 0x97e3 0xe3d 0x4c1d 0x9797 0xe39 0x4f28 0x974e 0xe36 0x5234 0x9708 0xe33 0x553f 0x96c5 0xe31 0x584a 0x9685 0xe30 0x5b56 0x9649 0xe30 0x5e61 0x9610 0xe2f 0x616d 0x95da 0xe2d 0x6478 0x95a6 0xe2f 0x6783 0x9578 0xe35 0x6a8f 0x954b 0xe3b 0x6d9a 0x951f 0xe3c 0x70a6 0x94f5 0xe40 0x73b1 0x94cd 0xe43 0x76bc 0x94aa 0xe02 0x79c8 0x94b1 0xe51 0x7cd3 0x947e 0xe61 0x7fdf 0x9455 0xe6e 0x82ea 0x9432 0xe7c 0x85f5 0x9414 0xe8a 0x8901 0x93f8 0xe98 0x8c0c 0x93df 0xea6 0x8f18 0x93c9 0xeb4 0x9223 0x93b3 0xec5 0x952e 0x939e 0xedb 0x983a 0x9389 0xef5 0x9b45 0x9374 0xf0c 0x9e50 0x935d 0xf23 0xa15c 0x9345 0xf3c 0xa467 0x932d 0xe56 0xa773 0x938b 0xef3 0xaa7e 0x9352 0xf3f 0xad89 0x9318 0xf7c 0xb095 0x92e6 0xfae 0xb3a0 0x92b9 0xfe0 0xb6ac 0x928e 0x1014 0xb9b7 0x9264 0x1047 0xbcc2 0x9234 0x1077 0xbfce 0x9202 0x10af 0xc2d9 0x91cc 0x10eb 0xc5e5 0x9195 0x112e 0xc8f0 0x915f 0x1179 0xcbfb 0x912f 0x11ce 0xcf07 0x9104 0x1231 0xd212 0x90de 0x1040 0xd51e 0x90eb 0x1057 0xd829 0x90c5 0x11da 0xdb34 0x907f 0x127a 0xde40 0x903e 0x124d 0xe14b 0x8fdf 0x120e 0xe457 0x8f32 0x1199 0xe762 0x8df3 0x10c1 0xea6d 0x8d7c 0x1071 0xed79 0x8a70 0xe61 0xf084 0x87b2 0xc86 0xf390 0x84b2 0xa7d 0xf69b 0x84b2 0xa7d 0xf9a6 0x84b2 0xa7d 0xfcb2 0x84b2 0xa7d 0xffbd 0x84b2 0xa7d 0x102c8 0x84b2 0xa7d 0x105d4 0x84b2 0xa7d 0x108df 0x84b2 0xa7d 0x10beb 0x84b2 0xa7d 0x10ef6 0x84b2 0xa7d 0x11201 0x84b2 0xa7d 0x1150d 0x84b2 0xa7d 0x11818 0x84b2 0xa7d 0x11b24 0x84b2 0xa7d 0x11e2f 0x84b2 0xa7d 0x1213a 0x84b2 0xa7d 0x12446 0x84b2 0xa7d 0x12751 0x84b2 0xa7d 0x12a5d 0x84b2 0xa7d 0x12d68 0x84b2 0xa7d>;
Q_MAX_SYS_VOLTAGE_BAT3 = <0xd48>;
g_FG_PSEUDO100_T4 = <0x64>;
battery0_profile_t0_num = <0x64>;
phandle = <0xa6>;
TEMPERATURE_T1 = <0x19>;
R_FG_VALUE = <0x05>;
POWERON_SYSTEM_IBOOT = <0x1f4>;
battery0_profile_t3_num = <0x64>;
TEMPERATURE_T3 = <0x00>;
compatible = "mediatek,bat_gm30";
battery0_profile_t1 = <0x00 0xa988 0x00 0x30b 0xa8b7 0x332 0x617 0xa810 0x332 0x922 0xa777 0x333 0xc2e 0xa6f4 0x335 0xf39 0xa666 0x32b 0x1244 0xa5eb 0x32d 0x1550 0xa573 0x332 0x185b 0xa4fd 0x334 0x1b67 0xa48f 0x335 0x1e72 0xa41b 0x335 0x217d 0xa3a8 0x338 0x2489 0xa334 0x338 0x2794 0xa2c0 0x33d 0x2aa0 0xa253 0x33f 0x2dab 0xa1ea 0x344 0x30b6 0xa181 0x34c 0x33c2 0xa118 0x353 0x36cd 0xa0a5 0x34d 0x39d8 0xa03b 0x353 0x3ce4 0x9fd2 0x354 0x3fef 0x9f76 0x35b 0x42fb 0x9f31 0x364 0x4606 0x9f05 0x37b 0x4911 0x9ec5 0x38e 0x4c1d 0x9e45 0x385 0x4f28 0x9d7d 0x37c 0x5234 0x9ccb 0x37f 0x553f 0x9c41 0x383 0x584a 0x9bd3 0x383 0x5b56 0x9b80 0x387 0x5e61 0x9b43 0x385 0x616d 0x9b16 0x391 0x6478 0x9aec 0x397 0x6783 0x9aba 0x39c 0x6a8f 0x9a74 0x398 0x6d9a 0x9a2a 0x391 0x70a6 0x99d6 0x38a 0x73b1 0x9982 0x383 0x76bc 0x992d 0x382 0x79c8 0x98cd 0x373 0x7cd3 0x9864 0x365 0x7fdf 0x97ff 0x357 0x82ea 0x97a8 0x349 0x85f5 0x9750 0x33f 0x8901 0x9706 0x33a 0x8c0c 0x96c1 0x332 0x8f18 0x9682 0x335 0x9223 0x9643 0x331 0x952e 0x9610 0x333 0x983a 0x95df 0x338 0x9b45 0x95aa 0x338 0x9e50 0x9576 0x333 0xa15c 0x9549 0x337 0xa467 0x9528 0x338 0xa773 0x94ff 0x33f 0xaa7e 0x94d5 0x338 0xad89 0x94bf 0x346 0xb095 0x9495 0x346 0xb3a0 0x9476 0x346 0xb6ac 0x9458 0x348 0xb9b7 0x943e 0x353 0xbcc2 0x941a 0x353 0xbfce 0x9405 0x351 0xc2d9 0x93ec 0x34f 0xc5e5 0x93cc 0x353 0xc8f0 0x93b7 0x350 0xcbfb 0x93a1 0x349 0xcf07 0x9381 0x342 0xd212 0x936f 0x348 0xd51e 0x934f 0x348 0xd829 0x933c 0x350 0xdb34 0x9319 0x348 0xde40 0x9300 0x352 0xe14b 0x92d8 0x353 0xe457 0x92ae 0x35a 0xe762 0x928e 0x34d 0xea6d 0x9266 0x34d 0xed79 0x924e 0x353 0xf084 0x9224 0x352 0xf390 0x91fa 0x34d 0xf69b 0x91cd 0x34d 0xf9a6 0x9199 0x351 0xfcb2 0x9164 0x35f 0xffbd 0x9130 0x365 0x102c8 0x90f1 0x364 0x105d4 0x90a2 0x35c 0x108df 0x9060 0x357 0x10beb 0x903f 0x367 0x10ef6 0x9031 0x378 0x11201 0x9026 0x390 0x1150d 0x9014 0x3ad 0x11818 0x8fe5 0x3c9 0x11b24 0x8f7a 0x3ec 0x11e2f 0x8e4f 0x3bb 0x1213a 0x8c82 0x3c0 0x12446 0x8a1c 0x3e5 0x12751 0x86c0 0x420 0x12a5d 0x8159 0x4d9 0x12d68 0x7aa8 0x3c6>;
Q_MAX_SYS_VOLTAGE_BAT0 = <0xd48>;
g_FG_PSEUDO100_T1 = <0x64>;
PMIC_MIN_VOL = <0x84d0>;
FG_METER_RESISTANCE = <0x4b>;
battery0_profile_t3 = <0x00 0xa923 0x00 0x30b 0xa7ff 0x717 0x617 0xa731 0x737 0x922 0xa688 0x744 0xc2e 0xa5f5 0x749 0xf39 0xa56f 0x74d 0x1244 0xa4f1 0x74e 0x1550 0xa47a 0x751 0x185b 0xa406 0x753 0x1b67 0xa395 0x752 0x1e72 0xa327 0x753 0x217d 0xa2b9 0x757 0x2489 0xa24b 0x758 0x2794 0xa1de 0x75a 0x2aa0 0xa170 0x760 0x2dab 0xa103 0x76e 0x30b6 0xa09b 0x771 0x33c2 0xa037 0x770 0x36cd 0x9fe5 0x774 0x39d8 0x9fae 0x784 0x3ce4 0x9f80 0x799 0x3fef 0x9f32 0x79e 0x42fb 0x9ea4 0x790 0x4606 0x9dd6 0x775 0x4911 0x9cf9 0x75c 0x4c1d 0x9c4a 0x757 0x4f28 0x9bc9 0x758 0x5234 0x9b64 0x75a 0x553f 0x9b10 0x75d 0x584a 0x9ac9 0x761 0x5b56 0x9a8e 0x765 0x5e61 0x9a5a 0x769 0x616d 0x9a2a 0x76c 0x6478 0x99f3 0x769 0x6783 0x99b2 0x761 0x6a8f 0x9967 0x756 0x6d9a 0x9915 0x74a 0x70a6 0x991e 0x74f 0x73b1 0x9891 0x74d 0x76bc 0x9823 0x744 0x79c8 0x97c7 0x73c 0x7cd3 0x9776 0x739 0x7fdf 0x972a 0x735 0x82ea 0x96e4 0x735 0x85f5 0x96a5 0x715 0x8901 0x9668 0x6e5 0x8c0c 0x962f 0x701 0x8f18 0x95f9 0x6ff 0x9223 0x95c7 0x6fe 0x952e 0x959a 0x707 0x983a 0x956f 0x712 0x9b45 0x9545 0x718 0x9e50 0x951e 0x71c 0xa15c 0x94f7 0x723 0xa467 0x94d4 0x736 0xa773 0x94b0 0x741 0xaa7e 0x9491 0x74c 0xad89 0x9471 0x755 0xb095 0x9454 0x75c 0xb3a0 0x943a 0x762 0xb6ac 0x9431 0x77a 0xb9b7 0x940e 0x790 0xbcc2 0x93f3 0x7a0 0xbfce 0x93dc 0x7ad 0xc2d9 0x93c9 0x7b7 0xc5e5 0x93b8 0x7c2 0xc8f0 0x93a9 0x7cc 0xcbfb 0x9399 0x7d6 0xcf07 0x9389 0x7e1 0xd212 0x9377 0x7ee 0xd51e 0x9363 0x7fc 0xd829 0x934e 0x80c 0xdb34 0x9337 0x81a 0xde40 0x931d 0x829 0xe14b 0x9302 0x839 0xe457 0x9318 0x7e7 0xe762 0x92db 0x813 0xea6d 0x92b2 0x83b 0xed79 0x9285 0x85d 0xf084 0x9254 0x87d 0xf390 0x921e 0x8a0 0xf69b 0x91e8 0x8c4 0xf9a6 0x91b0 0x8ea 0xfcb2 0x9170 0x910 0xffbd 0x9128 0x936 0x102c8 0x90e4 0x960 0x105d4 0x90b3 0x998 0x108df 0x9094 0x9e3 0x10beb 0x907b 0xa3f 0x10ef6 0x9061 0xaae 0x11201 0x9069 0x944 0x1150d 0x9025 0x979 0x11818 0x8f57 0xa44 0x11b24 0x8dbf 0xb32 0x11e2f 0x8b86 0xc96 0x1213a 0x8882 0xd13 0x12446 0x8453 0xa3f 0x12751 0x8073 0x7a2 0x12a5d 0x8073 0x7a2 0x12d68 0x8073 0x7a2>;
Q_MAX_SYS_VOLTAGE_BAT2 = <0xd48>;
g_FG_PSEUDO100_T3 = <0x64>;
PMIC_SHUTDOWN_CURRENT = <0x14>;
battery0_profile_t2_num = <0x64>;
DIFFERENCE_FULLOCV_ITH = <0x96>;
TEMPERATURE_T0 = <0x32>;
TEMPERATURE_T2 = <0x0a>;
battery0_profile_t1_num = <0x64>;
CAR_TUNE_VALUE = <0x64>;
TEMPERATURE_T4 = <0xfffffff6>;
battery0_profile_t0 = <0x00 0xa9a4 0x00 0x30b 0xa8f0 0x323 0x617 0xa852 0x323 0x922 0xa7c5 0x325 0xc2e 0xa73e 0x325 0xf39 0xa6bc 0x324 0x1244 0xa63f 0x322 0x1550 0xa5c5 0x323 0x185b 0xa54d 0x323 0x1b67 0xa4d8 0x325 0x1e72 0xa465 0x327 0x217d 0xa3f2 0x329 0x2489 0xa37f 0x328 0x2794 0xa30d 0x328 0x2aa0 0xa283 0x32b 0x2dab 0xa20b 0x32e 0x30b6 0xa1a2 0x333 0x33c2 0xa136 0x335 0x36cd 0xa0ca 0x337 0x39d8 0xa060 0x336 0x3ce4 0x9ff7 0x336 0x3fef 0x9f90 0x33a 0x42fb 0x9f2a 0x342 0x4606 0x9ec7 0x341 0x4911 0x9e66 0x344 0x4c1d 0x9e06 0x347 0x4f28 0x9da7 0x348 0x5234 0x9d47 0x349 0x553f 0x9ce8 0x34b 0x584a 0x9c8f 0x34e 0x5b56 0x9c3a 0x351 0x5e61 0x9be4 0x353 0x616d 0x9b93 0x358 0x6478 0x9b42 0x35d 0x6783 0x9af1 0x360 0x6a8f 0x9aa1 0x364 0x6d9a 0x9a53 0x365 0x70a6 0x9a02 0x361 0x73b1 0x99b1 0x36c 0x76bc 0x995a 0x36b 0x79c8 0x98f6 0x364 0x7cd3 0x9885 0x356 0x7fdf 0x9813 0x348 0x82ea 0x97ac 0x33e 0x85f5 0x9756 0x338 0x8901 0x970b 0x334 0x8c0c 0x96c9 0x332 0x8f18 0x968b 0x332 0x9223 0x9652 0x332 0x952e 0x961b 0x331 0x983a 0x95e7 0x331 0x9b45 0x95b5 0x332 0x9e50 0x9589 0x335 0xa15c 0x955c 0x336 0xa467 0x9531 0x338 0xa773 0x9508 0x33a 0xaa7e 0x94e1 0x33c 0xad89 0x94bb 0x33e 0xb095 0x9496 0x340 0xb3a0 0x9473 0x341 0xb6ac 0x9452 0x343 0xb9b7 0x9433 0x343 0xbcc2 0x9415 0x346 0xbfce 0x93f8 0x347 0xc2d9 0x93dc 0x34a 0xc5e5 0x93c1 0x34c 0xc8f0 0x93a6 0x34e 0xcbfb 0x9387 0x34c 0xcf07 0x935f 0x349 0xd212 0x9320 0x33e 0xd51e 0x92d3 0x335 0xd829 0x9293 0x334 0xdb34 0x9267 0x339 0xde40 0x923c 0x33b 0xe14b 0x920e 0x33a 0xe457 0x91df 0x338 0xe762 0x91b9 0x338 0xea6d 0x9197 0x33a 0xed79 0x9178 0x33c 0xf084 0x9155 0x33e 0xf390 0x9128 0x33e 0xf69b 0x90f3 0x33c 0xf9a6 0x90ba 0x33b 0xfcb2 0x9085 0x33b 0xffbd 0x904e 0x33e 0x102c8 0x9007 0x33d 0x105d4 0x8fc5 0x339 0x108df 0x8fa7 0x339 0x10beb 0x8f9d 0x33f 0x10ef6 0x8f91 0x345 0x11201 0x8f81 0x34c 0x1150d 0x8f64 0x355 0x11818 0x8eff 0x359 0x11b24 0x8ddb 0x352 0x11e2f 0x8c28 0x357 0x1213a 0x89e9 0x35f 0x12446 0x86de 0x378 0x12751 0x8262 0x3a8 0x12a5d 0x7b39 0x3fc 0x12d68 0x79b2 0x30e>;
SHUTDOWN_1_TIME = <0x3c>;
g_FG_PSEUDO100_T0 = <0x64>;
};
rt5081_pmu_eint {
phandle = <0xbb>;
};
scp_mad@105c1000 {
reg = <0x00 0x105c1000 0x00 0x1000>;
compatible = "mediatek,scp_mad";
};
dwrap1@878c0000 {
reg = <0x00 0x878c0000 0x00 0x1000>;
compatible = "mediatek,dwrap1";
};
touch {
tpd-filter-pixel-density = <0x92>;
phandle = <0xa4>;
tpd-key-num = <0x03>;
status = "okay";
pinctrl-1 = <0x10c>;
tpd-filter-enable = <0x01>;
compatible = "mediatek,touch";
pinctrl-3 = <0x10e>;
vtouch-supply = <0x8a>;
pinctrl-5 = <0x110>;
tpd-resolution = <0x320 0x500>;
tpd-key-dim-local = <0x5a 0x373 0x64 0x28 0xe6 0x373 0x64 0x28 0x172 0x373 0x64 0x28 0x00 0x00 0x00 0x00>;
use-tpd-button = <0x00>;
tpd-filter-custom-prameters = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
tpd-filter-custom-speed = <0x00 0x00 0x00>;
pinctrl-0 = <0x10b>;
tpd-max-touch-num = <0x05>;
pinctrl-2 = <0x10d>;
tpd-key-local = <0x8b 0xac 0x9e 0x00>;
pinctrl-names = "default\0state_eint_as_int\0state_eint_output0\0state_eint_output1\0state_rst_output0\0state_rst_output1";
pinctrl-4 = <0x10f>;
};
mt_soc_dl2_pcm {
compatible = "mediatek,mt_soc_pcm_dl2";
};
iocfg_0@11f20000 {
phandle = <0x1f>;
reg = <0x00 0x11f20000 0x00 0x1000>;
compatible = "mediatek,iocfg_0\0syscon";
};
kd_camera_hw1@1a040000 {
pinctrl-14 = <0xf5>;
pinctrl-6 = <0xed>;
pinctrl-16 = <0xf7>;
vcamio_sub-supply = <0x76>;
pinctrl-8 = <0xef>;
pinctrl-18 = <0xf9>;
phandle = <0xac>;
status = "okay";
pinctrl-1 = <0xe8>;
pinctrl-11 = <0xf2>;
vcamd_sub-supply = <0x77>;
compatible = "mediatek,imgsensor";
vcamio-supply = <0x76>;
pinctrl-3 = <0xea>;
pinctrl-13 = <0xf4>;
pinctrl-5 = <0xec>;
pinctrl-15 = <0xf6>;
vcama_sub-supply = <0x83>;
pinctrl-7 = <0xee>;
pinctrl-17 = <0xf8>;
pinctrl-9 = <0xf0>;
vcamd-supply = <0x77>;
pinctrl-19 = <0xfa>;
pinctrl-0 = <0xe7>;
pinctrl-10 = <0xf1>;
pinctrl-20 = <0xfb>;
pinctrl-2 = <0xe9>;
vcama-supply = <0x83>;
pinctrl-12 = <0xf3>;
pinctrl-names = "default\0cam0_rst0\0cam0_rst1\0cam0_pnd0\0cam0_pnd1\0cam1_rst0\0cam1_rst1\0cam1_pnd0\0cam1_pnd1\0cam0_mclk_off\0cam0_mclk_2mA\0cam0_mclk_4mA\0cam0_mclk_6mA\0cam0_mclk_8mA\0cam1_mclk_off\0cam1_mclk_2mA\0cam1_mclk_4mA\0cam1_mclk_6mA\0cam1_mclk_8mA\0cam_ldo_vcamaf_1\0cam_ldo_vcamaf_0";
pinctrl-4 = <0xeb>;
};
upa@f0920000 {
reg = <0x00 0xf0920000 0x00 0x1000>;
compatible = "mediatek,upa";
};
rxdfe@87860000 {
reg = <0x00 0x87860000 0x00 0x1000>;
compatible = "mediatek,rxdfe";
};
amms_control {
compatible = "mediatek,amms";
interrupts = <0x00 0x132 0x01>;
};
mdp_ccorr@1401c000 {
phandle = <0x39>;
reg = <0x00 0x1401c000 0x00 0x1000>;
compatible = "mediatek,mdp_ccorr";
clocks = <0x2f 0x2c>;
interrupts = <0x00 0xf3 0x08>;
clock-names = "MDP_CCORR";
};
hspasys_4_mbist@878b0000 {
reg = <0x00 0x878b0000 0x00 0x1000>;
compatible = "mediatek,hspasys_4_mbist";
};
mbist@17040000 {
reg = <0x00 0x17040000 0x00 0x1000>;
compatible = "mediatek,mbist";
};
apxgpt@10008000 {
reg = <0x00 0x10008000 0x00 0x100>;
compatible = "mediatek,apxgpt";
clocks = <0x2b>;
interrupts = <0x00 0xb0 0x08>;
};
msdc@11240000 {
sd-uhs-sdr12;
sd-uhs-sdr50;
pinctl_sdr104 = <0x17>;
host_function = [01];
register_setting = <0x1a>;
cd-gpios = <0x1b 0x03 0x00>;
max-frequency = <0xbebc200>;
sd-uhs-sdr104;
phandle = <0x50>;
reg = <0x00 0x11240000 0x00 0x10000>;
pinctl_ddr50 = <0x19>;
pinctl = <0x16>;
status = "okay";
pinctl_sdr50 = <0x18>;
compatible = "mediatek,msdc";
hw_dvfs = [00];
index = [01];
vmmc-supply = <0x1c>;
cd_level = [01];
clocks = <0x15 0x29 0x15 0x1e>;
interrupts = <0x00 0x4e 0x08>;
bus-width = <0x04>;
sd-uhs-sdr25;
vqmmc-supply = <0x1d>;
cap-sd-highspeed;
clock-names = "msdc1-clock\0msdc1-hclock";
clk_src = [04];
sd-uhs-ddr50;
msdc1@register_default {
phandle = <0x1a>;
wdata_edge = [00];
rdata_edge = [00];
cmd_edge = [00];
};
msdc1@sdr50 {
phandle = <0x18>;
pins_cmd {
drive-strength = [03];
};
pins_clk {
drive-strength = [03];
};
pins_dat {
drive-strength = [03];
};
};
msdc1@default {
phandle = <0x16>;
pins_cmd {
drive-strength = [03];
};
pins_clk {
drive-strength = [03];
};
pins_dat {
drive-strength = [03];
};
};
msdc1@ddr50 {
phandle = <0x19>;
pins_cmd {
drive-strength = [03];
};
pins_clk {
drive-strength = [03];
};
pins_dat {
drive-strength = [03];
};
};
msdc1@sdr104 {
phandle = <0x17>;
pins_cmd {
drive-strength = [03];
};
pins_clk {
drive-strength = [03];
};
pins_dat {
drive-strength = [03];
};
};
};
usb_boost_manager {
phandle = <0xa1>;
compatible = "mediatek,usb_boost";
boost_period = <0x1e>;
};
h_txbrp@876a0000 {
reg = <0x00 0x876a0000 0x00 0x1000>;
compatible = "mediatek,h_txbrp";
};
seninf3@1a042000 {
reg = <0x00 0x1a042000 0x00 0x1000>;
compatible = "mediatek,seninf3";
};
md_cirq@f0070000 {
reg = <0x00 0xf0070000 0x00 0x1000>;
compatible = "mediatek,md_cirq";
};
venc_gcon@17000000 {
phandle = <0x48>;
reg = <0x00 0x17000000 0x00 0x1000>;
compatible = "mediatek,venc_gcon\0syscon";
#clock-cells = <0x01>;
};
dispsys {
compatible = "mediatek,dispsys";
clocks = <0x2e 0x03 0x2f 0x01 0x2f 0x02 0x2f 0x03 0x2f 0x04 0x2f 0x05 0x2f 0x14 0x2f 0x15 0x2f 0x16 0x2f 0x17 0x2f 0x18 0x2f 0x19 0x2f 0x1a 0x2f 0x1b 0x2f 0x1c 0x2f 0x1d 0x2f 0x1e 0x2f 0x20 0x2f 0x21 0x2f 0x22 0x2f 0x23 0x2f 0x2d 0x2f 0x2e 0x2f 0x27 0x2f 0x29 0x42 0x02 0x42 0x16 0x15 0x36 0x2c 0x42 0x43 0x42 0x44 0x42 0x5c 0x42 0x5d 0x42 0x5f 0x42 0x12 0x42 0x52 0x42 0x53 0x42 0x54 0x42 0x55 0x42 0x51>;
clock-names = "MMSYS_MTCMOS\0MMSYS_SMI_COMMON\0MMSYS_SMI_LARB0\0MMSYS_SMI_LARB1\0MMSYS_GALS_COMM0\0MMSYS_GALS_COMM1\0MMSYS_DISP_OVL0\0MMSYS_DISP_OVL0_2L\0MMSYS_DISP_OVL1_2L\0MMSYS_DISP_RDMA0\0MMSYS_DISP_RDMA1\0MMSYS_DISP_WDMA0\0MMSYS_DISP_COLOR0\0MMSYS_DISP_CCORR0\0MMSYS_DISP_AAL0\0MMSYS_DISP_GAMMA0\0MMSYS_DISP_DITHER0\0MMSYS_DSI0_MM_CK\0MMSYS_DSI0_IF_CK\0MMSYS_DPI_MM_CK\0MMSYS_DPI_IF_CK\0MMSYS_DBI_MM_CK\0MMSYS_DBI_IF_CK\0MMSYS_26M\0MMSYS_DISP_RSZ\0TOP_MUX_MM\0TOP_MUX_DISP_PWM\0DISP_PWM\0TOP_26M\0TOP_UNIVPLL_D3_D2\0TOP_UNIVPLL_D3_D4\0TOP_OSC_D2\0TOP_OSC_D4\0TOP_OSC_D16\0MUX_DPI0\0TVDPLL_D2\0TVDPLL_D4\0TVDPLL_D8\0TVDPLL_D16\0DPI_CK";
};
camsv6@1a055000 {
reg = <0x00 0x1a055000 0x00 0x1000>;
compatible = "mediatek,camsv6";
};
imgsys1_dfp@1502e000 {
reg = <0x00 0x1502e000 0x00 0x1000>;
compatible = "mediatek,imgsys1_dfp";
};
a7_wdt@f0400000 {
reg = <0x00 0xf0400000 0x00 0x1000>;
compatible = "mediatek,a7_wdt";
};
l2c@10f00000 {
reg = <0x00 0x10f00000 0x00 0x1000>;
compatible = "mediatek,l2c";
};
mt_soc_i2s0dl1_pcm {
compatible = "mediatek,mt_soc_pcm_dl1_i2s0dl1";
};
apcldmaout_ao@10014400 {
reg = <0x00 0x10014400 0x00 0x1000>;
compatible = "mediatek,apcldmaout_ao";
};
hwrng {
phandle = <0x93>;
compatible = "mediatek,mt67xx-rng";
};
hspasys_1_confg@87200000 {
reg = <0x00 0x87200000 0x00 0x1000>;
compatible = "mediatek,hspasys_1_confg";
};
mmsys_config@14000000 {
phandle = <0x2f>;
reg = <0x00 0x14000000 0x00 0x1000>;
compatible = "mediatek,mmsys_config\0syscon";
#clock-cells = <0x01>;
clocks = <0x2f 0x0b 0x2f 0x25 0x2f 0x0c 0x2f 0x26>;
interrupts = <0x00 0xef 0x08>;
clock-names = "CAM_MDP_TX\0CAM_MDP_RX\0CAM_MDP2_TX\0CAM_MDP2_RX";
};
dma-controller@11000780 {
#dma-cells = <0x01>;
phandle = <0x41>;
reg = <0x00 0x11000780 0x00 0x80 0x00 0x11000800 0x00 0x80 0x00 0x11000880 0x00 0x80 0x00 0x11000900 0x00 0x80 0x00 0x11000980 0x00 0x80 0x00 0x11000a00 0x00 0x80>;
compatible = "mediatek,mt6577-uart-dma";
clocks = <0x15 0x2b>;
interrupts = <0x00 0x6c 0x08 0x00 0x6d 0x08 0x00 0x6e 0x08 0x00 0x6f 0x08 0x00 0x70 0x08 0x00 0x71 0x08>;
dma-bits = <0x22>;
clock-names = "apdma";
};
scp_intc@105c2000 {
reg = <0x00 0x105c2000 0x00 0x1000>;
compatible = "mediatek,scp_intc";
};
a7_ost@f0160000 {
reg = <0x00 0xf0160000 0x00 0x1000>;
compatible = "mediatek,a7_ost";
};
dip3@15024000 {
reg = <0x00 0x15024000 0x00 0x1000>;
compatible = "mediatek,dip3";
};
gce@10238000 {
disp_2l_ovl1_sof = <0x0b>;
mdp_rsz0 = <0x33>;
disp_ovl0_2l_frame_rst_done_pusle = <0x9c>;
mmsys_config_base = <0x14000000 0x01 0xffff0000>;
buf_underrun_event_1 = <0x8f>;
camsv_2_pass1_done = <0x145>;
mdp_rsz1_frame_done = <0x1f>;
secure_thread = <0x08 0x0a>;
mdp_wdma_frame_done = <0x22>;
wmf_frame_done = <0x116>;
dip_cq_thread9_frame_done = <0x10a>;
jpgenc_done = <0x122>;
mdp_rsz0_sof = <0x04>;
mdp_aal_frame_done = <0x30>;
disp_pwm0_sof = <0x12>;
stream_done_0 = <0x82>;
sram_share_cnt = <0x01>;
disp_dither0_frame_done = <0x2b>;
vdec1_base = <0x17030000 0x15 0xffff0000>;
dip_cq_thread4_frame_done = <0x105>;
disp_rsz0_frame_done = <0x2f>;
mdp_ccorr0 = <0x39>;
seninf_5_fifo_full = <0x14c>;
seninf_0_fifo_full = <0x147>;
tsf_done = <0x146>;
msdc2_base = <0x17020000 0x14 0xffff0000>;
camsys2_base = <0x180b0000 0x1d 0xffff0000>;
vdec_base = <0x17010000 0x13 0xffff0000>;
ipu_done_1_1 = <0x182>;
pwm_sw_base = <0x11000000 0x63 0xffff0000>;
disp_rdma0_sof = <0x00>;
rsc_frame_done = <0x117>;
stream_done_2 = <0x84>;
disp_mutex_reg = <0x14016000 0x1000>;
mdp_rdma0_rst_done = <0x9a>;
dip_cq_thread14_frame_done = <0x10f>;
venc = <0x3b>;
mboxes = <0x40 0x00 0x00 0x04 0x40 0x01 0x00 0x04 0x40 0x02 0x00 0x05 0x40 0x03 0x00 0x04 0x40 0x04 0x00 0x04 0x40 0x05 0x00 0x04 0x40 0x06 0x00 0x03 0x40 0x07 0xffffffff 0x02 0x40 0x08 0x00 0x01 0x40 0x09 0x00 0x01 0x40 0x0a 0x00 0x01 0x40 0x0b 0x00 0x01 0x40 0x0c 0x00 0x01 0x40 0x0d 0x00 0x01 0x40 0x0e 0x00 0x01 0x40 0x0f 0x00 0x01>;
uart = <0x3e>;
mdp_wrot0 = <0x35>;
disp_aal0_sof = <0x0f>;
wpe_a_frame_done = <0x119>;
ipu_done_1_3 = <0x184>;
mdp_ccorr_frame_done = <0x31>;
vdec2_base = <0x18040000 0x19 0xffff0000>;
reg = <0x00 0x10238000 0x00 0x4000>;
stream_done_4 = <0x86>;
disp_2l_ovl0_sof = <0x0a>;
conn_peri_base = <0x18820000 0x07 0xffff0000>;
dip_cq_thread6_frame_done = <0x107>;
mdp_tdshp_frame_done = <0x20>;
mmsys_config = <0x2f>;
venc_gcon_base = <0x18810000 0x06 0xffff0000>;
disp_2l_ovl1_frame_done = <0x25>;
msdc3_base = <0x18000000 0x16 0xffff0000>;
disp_ccorr0_sof = <0x0e>;
gce_base = <0x18020000 0x18 0xffff0000>;
dip_cq_thread1_frame_done = <0x102>;
scp_sram_base = <0x10000000 0x0a 0xffff0000>;
ipu_done_0 = <0x161>;
amd_frame_done = <0x114>;
seninf_7_fifo_full = <0x14e>;
g3d_config_base = <0x13000000 0x00 0xffff0000>;
seninf_2_fifo_full = <0x149>;
disp_wdma0_sof = <0x0c>;
max_prefetch_cnt = <0x04>;
disp_dbi0_sof = <0x19>;
mdp_tdshp_sof = <0x06>;
mdp_aal0 = <0x38>;
mdp_wdma_sof = <0x08>;
mdp_rdma1 = <0x32>;
stream_done_6 = <0x88>;
topckgen_base = <0x18830000 0x08 0xffff0000>;
dip_cq_thread16_frame_done = <0x111>;
isp_frame_done_a = <0x141>;
compatible = "mediatek,gce";
stream_done_11 = <0x8d>;
infra_na3_base = <0x10010000 0x0b 0xffff0000>;
dip_cq_thread11_frame_done = <0x10c>;
vdec3_base = <0x18050000 0x1a 0xffff0000>;
disp_dither0_sof = <0x11>;
disp_ovl0_frame_done = <0x23>;
ipu_done_2 = <0x163>;
vdec_gcon_base = <0x18800000 0x05 0xffff0000>;
camsv_1_pass1_done = <0x144>;
stream_done_8 = <0x8a>;
mdp_rsz0_frame_done = <0x1e>;
disp_color0_sof = <0x0d>;
dip_cq_thread8_frame_done = <0x109>;
sram_share_event = <0x2c6>;
mdp_ccorr_sof = <0x18>;
mediatek,mailbox-gce = <0x40>;
buf_underrun_event_0 = <0x8e>;
mdp_aal_sof = <0x17>;
dsi0_irq_event = <0x91>;
disp_dbi0_frame_done = <0x32>;
disp_dpi0_sof = <0x14>;
dip_cq_thread3_frame_done = <0x104>;
camsys_base = <0x18080000 0x1b 0xffff0000>;
ap_dma_base = <0x18010000 0x17 0xffff0000>;
mdp_wdma0 = <0x36>;
disp_gamma0_sof = <0x10>;
seninf_4_fifo_full = <0x14b>;
disp_dpi0_frame_done = <0x2d>;
dip_cq_thread18_frame_done = <0x113>;
infra_na4_base = <0x10020000 0x0c 0xffff0000>;
msdc0 = <0x3c>;
disp_rdma1_frame_done = <0x1b>;
mdp_rsz1 = <0x34>;
disp_ovl1_2l_frame_rst_done_pusle = <0x9d>;
prefetch_size = <0xa0 0x20 0x20 0x20>;
dip_cq_thread13_frame_done = <0x10e>;
sram_share_engine = <0x18>;
mm_na_base = <0x14020000 0x03 0xffff0000>;
ipu_done_1_0 = <0x181>;
mm_mutex = <0x30>;
mdp_rdma0_sof = <0x02>;
disp_dsi0_frame_done = <0x2c>;
jpgdec_done = <0x123>;
smi_larb0 = <0x3f>;
stream_done_1 = <0x83>;
clocks = <0x15 0x09 0x15 0x19>;
interrupts = <0x00 0xa2 0x08 0x00 0xa3 0x08>;
disp_dsi0_sof = <0x13>;
disp_wdma0_rst_done = <0x96>;
disp_aal0_frame_done = <0x29>;
mdp_tdshp0 = <0x37>;
disp_ccorr0_frame_done = <0x28>;
mdp_wdma_rst_done = <0x97>;
dip_cq_thread5_frame_done = <0x106>;
disp_2l_ovl0_frame_done = <0x24>;
ipu_done_1_2 = <0x183>;
stream_done_3 = <0x85>;
usb_sif_base = <0x10280000 0x11 0xffff0000>;
dip_cq_thread0_frame_done = <0x101>;
seninf_6_fifo_full = <0x14d>;
seninf_1_fifo_full = <0x148>;
scp_base = <0x10030000 0x0d 0xffff0000>;
disp_ovl0_sof = <0x09>;
dip_cq_thread15_frame_done = <0x110>;
dsi0_done_event = <0x92>;
clock-names = "GCE\0GCE_TIMER";
mdp_wrot0_sof = <0x07>;
mdp_rsz1_sof = <0x05>;
mdp_rdma0 = <0x31>;
stream_done_5 = <0x87>;
dip_cq_thread10_frame_done = <0x10b>;
venc_mb_done = <0x124>;
disp_ovl0_frame_rst_done_pusle = <0x9b>;
usb0_base = <0x10200000 0x10 0xffff0000>;
audio = <0x3d>;
occ_done = <0x11b>;
venc_done = <0x121>;
wpe_b_frame_done = <0x11a>;
disp_color0_frame_done = <0x27>;
stream_done_10 = <0x8c>;
disp_gamma0_frame_done = <0x2a>;
gcpu_base = <0x10050000 0x0f 0xffff0000>;
mcucfg_base = <0x10040000 0x0e 0xffff0000>;
dve_frame_done = <0x115>;
camsv_0_pass1_done = <0x143>;
mdp_wrot0_rst_done = <0x98>;
ipu_done_1 = <0x162>;
imgsys_base = <0x15020000 0x04 0xffff0000>;
dip_cq_thread7_frame_done = <0x108>;
mdp_color0 = <0x3a>;
sram_size_cpr_64 = <0x88>;
dsi0_te_event = <0x90>;
mdp_wrot0_write_frame_done = <0x21>;
disp_rdma1_sof = <0x01>;
stream_done_7 = <0x89>;
dip_cq_thread2_frame_done = <0x103>;
mdp_rdma0_frame_done = <0x1c>;
venc_128byte_cnt_done = <0x125>;
disp_rsz0_sof = <0x16>;
mfb_done = <0x118>;
seninf_3_fifo_full = <0x14a>;
isp_frame_done_b = <0x142>;
disp_wdma0_frame_done = <0x26>;
kp_base = <0x18840000 0x09 0xffff0000>;
dip_cq_thread17_frame_done = <0x112>;
ipu_done_3 = <0x164>;
disp_rdma0_frame_done = <0x1a>;
disp_dither_base = <0x14010000 0x02 0xffff0000>;
audio_base = <0x17000000 0x12 0xffff0000>;
camsys1_base = <0x180a0000 0x1c 0xffff0000>;
dip_cq_thread12_frame_done = <0x10d>;
stream_done_9 = <0x8b>;
};
hevc_vld@16028000 {
reg = <0x00 0x16028000 0x00 0x1000>;
compatible = "mediatek,hevc_vld";
};
scp_spi2@105d1000 {
reg = <0x00 0x105d1000 0x00 0x1000>;
compatible = "mediatek,scp_spi2";
};
mt_soc_voice_md2_bt {
compatible = "mediatek,mt_soc_pcm_voice_md2_bt";
};
mhl@0 {
phandle = <0xa9>;
compatible = "mediatek,extd_dev";
};
mdcldmain@1021c000 {
reg = <0x00 0x1021c000 0x00 0x1000>;
compatible = "mediatek,mdcldmain";
};
mt_soc_dai_name {
compatible = "mediatek,mt_soc_dai_stub";
};
ipu0@19180000 {
phandle = <0x4b>;
reg = <0x00 0x19180000 0x00 0x1000>;
compatible = "mediatek,ipu0\0syscon";
#clock-cells = <0x01>;
interrupts = <0x00 0x124 0x08>;
};
l2ulbuf@850e0000 {
reg = <0x00 0x850e0000 0x00 0x1000>;
compatible = "mediatek,l2ulbuf";
};
rfic1_bsispi@80202000 {
reg = <0x00 0x80202000 0x00 0x1000>;
compatible = "mediatek,rfic1_bsispi";
};
lk_charger {
power_path_support;
temp_t3_threshold = <0x2d>;
pd_charger_current = <0x7a120>;
usb_charger_current = <0x7a120>;
ac_charger_input_current = <0x155cc0>;
phandle = <0xb4>;
compatible = "mediatek,lk_charger";
ta_ac_charger_current = <0x2dc6c0>;
enable_pd20_reset;
fast_charge_voltage = <0x2dc6c0>;
max_charger_voltage = <0xa037a0>;
enable_pe_plus;
charging_host_charger_current = <0x16e360>;
temp_t4_threshold = <0x32>;
ac_charger_current = <0x1f47d0>;
enable_anime;
non_std_ac_charger_current = <0x1e8480>;
temp_t1_threshold = <0x00>;
};
charger {
temp_t0_thres_plus_x_degree = <0x00>;
cable_imp_threshold = <0x2bb>;
usb_charger_current_unconfigured = <0x11170>;
disable_pd_dual;
bif_cv_under_threshold2 = <0x43e6d0>;
ta_start_battery_soc = <0x00>;
pe40_r_cable_1a_lower = <0x1f4>;
jeita_temp_below_t0_cv = <0x3da540>;
jeita_temp_t1_to_t2_cv = <0x40b280>;
pd_vbus_low_bound = <0x4c4b40>;
power_path_support;
min_charger_voltage = <0x4630c0>;
pd_stop_battery_soc = <0x50>;
ta_9v_support;
bif_threshold1 = <0x40d990>;
ta_ac_12v_input_current = <0x16e360>;
apple_1_0a_charger_current = <0x9eb10>;
jeita_temp_t2_to_t3_cv = <0x423920>;
pe40_single_charger_input_current = <0x2dc6c0>;
usb_charger_current = <0x7a120>;
min_charge_temp_plus_x_degree = <0x06>;
temp_t4_thres_minus_x_degree = <0x2f>;
ta_stop_battery_soc = <0x55>;
temp_t1_thres = <0x00>;
ibus_err = <0x0e>;
temp_neg_10_thres = <0x00>;
ac_charger_input_current = <0x1e8480>;
phandle = <0xb5>;
high_temp_to_enter_pe40 = <0x27>;
pe40_dual_charger_chg1_current = <0x1e8480>;
enable_dynamic_mivr;
jeita_temp_t3_to_t4_cv = <0x40b280>;
pe20_ichg_level_threshold = <0xf4240>;
dual_polling_ieoc = <0x6ddd0>;
enable_min_charge_temp;
max_charge_temp_minus_x_degree = <0x2f>;
pe40_stop_battery_soc = <0x50>;
temp_t4_thres = <0x32>;
ta_ac_9v_input_current = <0x1e8480>;
compatible = "mediatek,charger";
low_temp_to_leave_pe40 = <0x0a>;
temp_t1_thres_plus_x_degree = <0x06>;
enable_pe_2;
min_charger_voltage_2 = <0x401640>;
enable_type_c;
ta_ac_charger_current = <0x2dc6c0>;
pd_ichg_level_threshold = <0xf4240>;
temp_t0_thres = <0x00>;
enable_pe_4;
chg2_ta_ac_charger_current = <0x1e8480>;
pe40_single_charger_current = <0x2dc6c0>;
usb_charger_current_configured = <0x7a120>;
max_charge_temp = <0x32>;
temp_t3_thres = <0x2d>;
pd_vbus_upper_bound = <0x4c4b40>;
max_charger_voltage = <0xa037a0>;
pe40_dual_charger_chg2_current = <0x1e8480>;
enable_pe_plus;
bif_threshold2 = <0x419ce0>;
charging_host_charger_current = <0x16e360>;
pe_ichg_level_threshold = <0xf4240>;
high_temp_to_leave_pe40 = <0x2e>;
min_charge_temp = <0x00>;
temp_t2_thres_plus_x_degree = <0x10>;
algorithm_name = "DualSwitchCharging";
max_dmivr_charger_current = <0x155cc0>;
ac_charger_current = <0x1f47d0>;
jeita_temp_above_t4_cv = <0x40b280>;
min_charger_voltage_1 = <0x432380>;
slave_mivr_diff = <0x186a0>;
chg1_ta_ac_charger_current = <0x1e8480>;
low_temp_to_enter_pe40 = <0x10>;
pe40_dual_charger_input_current = <0x2dc6c0>;
apple_2_1a_charger_current = "\0\f5";
non_std_ac_charger_current = <0x1e8480>;
jeita_temp_t0_to_t1_cv = <0x3da540>;
temp_t2_thres = <0x0a>;
pe40_r_cable_3a_lower = <0xf0>;
vbat_cable_imp_threshold = <0x3b8260>;
enable_pe_3;
battery_cv = <0x426030>;
vsys_watt = <0x4c4b40>;
temp_t3_thres_minus_x_degree = <0x27>;
usb_charger_current_suspend = <0x00>;
pe40_r_cable_2a_lower = <0x15f>;
ta_ac_7v_input_current = <0x1e8480>;
};
pf_bsi_apb2@80201000 {
reg = <0x00 0x80201000 0x00 0x1000>;
compatible = "mediatek,pf_bsi_apb2";
};
dbgapb@0d000000 {
reg = <0x00 0xd000000 0x00 0x1000>;
compatible = "mediatek,dbgapb";
};
serial@11002000 {
dmas = <0x41 0x00 0x41 0x01>;
phandle = <0x3e>;
reg = <0x00 0x11002000 0x00 0x1000>;
status = "okay";
pinctrl-1 = <0xcd>;
compatible = "mediatek,mt6577-uart";
pinctrl-3 = <0xcf>;
dma-names = "tx\0rx";
clocks = <0x2c 0x15 0x15>;
interrupts = <0x00 0x5b 0x08>;
clock-names = "baud\0bus";
pinctrl-0 = <0xcc>;
pinctrl-2 = <0xce>;
pinctrl-names = "uart0_gpio_default\0uart0_rx_set\0uart0_rx_clear\0uart0_tx_set\0uart0_tx_clear";
pinctrl-4 = <0xd0>;
};
utos_tester {
compatible = "microtrust,tester-v1";
};
patch@82cc0000 {
reg = <0x00 0x82cc0000 0x00 0x1000>;
compatible = "mediatek,patch";
};
wcdma_timer@870a0000 {
reg = <0x00 0x870a0000 0x00 0x1000>;
compatible = "mediatek,wcdma_timer";
};
usb0phy@11f40000 {
phandle = <0x43>;
reg = <0x00 0x11f40000 0x00 0x10000 0x00 0x11203e00 0x00 0x100>;
compatible = "mediatek,mt6771-phy";
#phy-cells = <0x01>;
reg-names = "sif_base\0ippc";
};
vdec@16020000 {
reg = <0x00 0x16020000 0x00 0x10000>;
compatible = "mediatek,vdec";
interrupts = <0x00 0xfa 0x08>;
};
hspasys_2_mbist@87440000 {
reg = <0x00 0x87440000 0x00 0x1000>;
compatible = "mediatek,hspasys_2_mbist";
};
eem_fsm@1100b000 {
reg = <0x00 0x1100b000 0x00 0x1000>;
compatible = "mediatek,eem_fsm";
interrupts = <0x00 0x7f 0x08>;
};
devapc_mpu_ao@10015000 {
reg = <0x00 0x10015000 0x00 0x1000>;
compatible = "mediatek,devapc_mpu_ao";
};
ap_ccif0@10209000 {
reg = <0x00 0x10209000 0x00 0x1000>;
compatible = "mediatek,ap_ccif0";
interrupts = <0x00 0x97 0x08>;
};
md_infra_busmon@80320000 {
reg = <0x00 0x80320000 0x00 0x1000>;
compatible = "mediatek,md_infra_busmon";
};
atf_logger {
compatible = "mediatek,atf_logger";
interrupts = <0x00 0xf5 0x01>;
};
md_rgu@f00f0000 {
reg = <0x00 0xf00f0000 0x00 0x1000>;
compatible = "mediatek,md_rgu";
interrupts = <0x00 0x11b 0x02>;
};
disp_pwm0@1100e000 {
reg = <0x00 0x1100e000 0x00 0x1000>;
compatible = "mediatek,disp_pwm0";
interrupts = <0x00 0x80 0x08>;
};
md_bus_recoder@803c0000 {
reg = <0x00 0x803c0000 0x00 0x1000>;
compatible = "mediatek,md_bus_recoder";
};
dpe_dma@15028000 {
reg = <0x00 0x15028000 0x00 0x1000>;
compatible = "mediatek,dpe_dma";
};
dpa_mac@87630000 {
reg = <0x00 0x87630000 0x00 0x1000>;
compatible = "mediatek,dpa_mac";
};
owe@1502c000 {
reg = <0x00 0x1502c000 0x00 0x1000>;
compatible = "mediatek,owe";
clocks = <0x49 0x01>;
interrupts = <0x00 0x115 0x08>;
clock-names = "OWE_CLK_IMG_OWE";
};
l2ullmac@85080000 {
reg = <0x00 0x85080000 0x00 0x1000>;
compatible = "mediatek,l2ullmac";
};
mdsmicfg@803a0000 {
reg = <0x00 0x803a0000 0x00 0x1000>;
compatible = "mediatek,mdsmicfg";
};
irtx@1100d000 {
reg = <0x00 0x1100d000 0x00 0x1000>;
compatible = "mediatek,irtx";
};
mt_soc_routing_pcm {
compatible = "mediatek,mt_soc_pcm_routing";
};
disp_aal0@14010000 {
phandle = <0xaa>;
reg = <0x00 0x14010000 0x00 0x1000>;
compatible = "mediatek,disp_aal0";
aal_support = <0x01>;
interrupts = <0x00 0xe9 0x08>;
};
1000b000.pinctrl {
interrupt-controller;
gpio-ranges = <0x1b 0x00 0x00 0xbf>;
#gpio-cells = <0x02>;
reg_bases = <0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26>;
phandle = <0x1b>;
reg_base_eint = <0x27>;
#interrupt-cells = <0x04>;
compatible = "mediatek,mt6771-pinctrl";
pins-are-numbered;
interrupts = <0x00 0xb1 0x04>;
gpio-controller;
hdmi_pins_funcmode {
phandle = <0x109>;
pins_cmd_dat {
pinmux = <0x3201 0x3301 0xaa01 0xab01 0xac01 0xd01 0xe01 0xf01 0x1001 0x1101 0x1201 0x1301 0x1401 0x1501 0x1601 0x1701 0x1801 0x1901 0x1a01 0x1b01 0x1c01>;
};
};
aud_clk_mosi_on {
phandle = <0xd2>;
pins_cmd0_dat {
pinmux = <0x8801>;
};
};
eintoutput1 {
phandle = <0x10e>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x100>;
output-high;
};
};
cam0@3 {
phandle = <0xeb>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x6100>;
output-high;
};
};
camdefault {
phandle = <0xe7>;
};
camera_pins_cam0_mclk_2ma {
phandle = <0xf1>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x00>;
};
};
camera_pins_cam1_mclk_6ma {
phandle = <0xf8>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x02>;
};
};
usb_default {
phandle = <0xfc>;
};
u3_sw_en {
phandle = <0x107>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1b00>;
};
};
rstoutput1 {
phandle = <0x110>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x9e00>;
output-high;
};
};
eint0default {
phandle = <0x10b>;
};
cam0@1 {
phandle = <0xe9>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x6500>;
output-high;
};
};
gpiokey_default {
phandle = <0x111>;
};
uart0_tx_set@gpio96 {
phandle = <0xcf>;
pins_cmd_dat {
pinmux = <0x6001>;
};
};
uart0_tx_clear@gpio96 {
phandle = <0xd0>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x6000>;
output-high;
};
};
alspsdefaultcfg {
phandle = <0xe3>;
};
camera_pins_cam0_mclk_8ma {
phandle = <0xf4>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x03>;
};
};
extamp_pullhigh {
phandle = <0xdd>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x4500>;
output-high;
};
};
cam1@2 {
phandle = <0xee>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x6200>;
};
};
camera_pins_cam1_mclk_2ma {
phandle = <0xf6>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x00>;
};
};
gpslna@2 {
phandle = <0xe2>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x9b00>;
};
};
id_disable {
phandle = <0x116>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1800>;
input-disable;
};
};
c1_highz {
phandle = <0xff>;
pins_cmd_dat {
slew-rate = <0x00>;
pinmux = <0x1500>;
bias-disable;
};
};
cam1@0 {
phandle = <0xec>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x6600>;
};
};
alspspincfg {
phandle = <0xe4>;
pins_cmd_dat {
bias-pull-up = <0x00>;
slew-rate = <0x00>;
pinmux = <0x600>;
};
};
camera_pins_cam0_mclk_off {
phandle = <0xf0>;
pins_cmd_dat {
pinmux = <0x6300>;
drive-strength = <0x01>;
};
};
aud_pins_smartpa_on {
phandle = <0xd8>;
pins_cmd0_dat {
pinmux = <0xae02>;
};
};
consys_default {
phandle = <0xdf>;
};
gpslna@0 {
phandle = <0xe0>;
pins_cmd_dat {
output-low;
slew-rate = <0x00>;
pinmux = <0x9b00>;
bias-disable;
};
};
camera_pins_cam0_vcamaf_off {
phandle = <0xfb>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0xa900>;
};
};
u3_sw_sel1 {
phandle = <0x105>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1c00>;
};
};
camera_pins_cam0_mclk_4ma {
phandle = <0xf2>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x01>;
};
};
u3_sw_dis {
phandle = <0x108>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x1b00>;
output-high;
};
};
camera_pins_cam1_mclk_8ma {
phandle = <0xf9>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x03>;
};
};
c2_init {
phandle = <0x101>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1600>;
};
};
aud_dat_miso_on {
phandle = <0xd6>;
pins_cmd1_dat {
pinmux = <0x8e01>;
};
pins_cmd2_dat {
pinmux = <0x8f01>;
};
};
vow_dat_miso_off {
phandle = <0xd9>;
pins_cmd1_dat {
pinmux = <0x8e00>;
};
};
irtx_gpio_led_def@gpio90 {
phandle = <0xe5>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
input-schmitt-enable = <0x00>;
pinmux = <0x5a00>;
bias-disable;
};
};
hdmi_pins_gpiomode {
phandle = <0x10a>;
pins_cmd_dat {
pinmux = <0xaa00 0xab00 0xac00 0xd00 0xe00 0xf00 0x1000 0x1100 0x1200 0x1300 0x1400 0x1500 0x1600 0x1700 0x1800 0x1900 0x1a00 0x1b00 0x1c00>;
};
};
eintoutput0 {
phandle = <0x10d>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x100>;
};
};
iddig_default {
phandle = <0x113>;
};
c2_high {
phandle = <0x104>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x1600>;
output-high;
};
};
vow_dat_miso_on {
phandle = <0xda>;
pins_cmd1_dat {
pinmux = <0x8e04>;
};
};
cam0@2 {
phandle = <0xea>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x6100>;
};
};
camera_pins_cam1_mclk_off {
phandle = <0xf5>;
pins_cmd_dat {
pinmux = <0x6300>;
drive-strength = <0x01>;
};
};
aud_dat_mosi_on {
phandle = <0xd4>;
pins_cmd1_dat {
pinmux = <0x8a01>;
};
pins_cmd2_dat {
pinmux = <0x8b01>;
};
};
eint@0 {
phandle = <0x10c>;
pins_cmd_dat {
slew-rate = <0x00>;
pinmux = <0x100>;
bias-disable;
};
};
rstoutput0 {
phandle = <0x10f>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x9e00>;
};
};
c1_init {
phandle = <0xfd>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1500>;
};
};
vow_clk_miso_off {
phandle = <0xdb>;
pins_cmd3_dat {
pinmux = <0x8f00>;
};
};
c2_highz {
phandle = <0x103>;
pins_cmd_dat {
slew-rate = <0x00>;
pinmux = <0x1600>;
bias-disable;
};
};
camera_pins_cam0_vcamaf_on {
phandle = <0xfa>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0xa900>;
output-high;
};
};
uart0gpiodefault {
phandle = <0xcc>;
};
aud_dat_miso_off {
phandle = <0xd5>;
pins_cmd1_dat {
pinmux = <0x8e00>;
};
pins_cmd2_dat {
pinmux = <0x8f00>;
};
};
camera_pins_cam1_mclk_4ma {
phandle = <0xf7>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x01>;
};
};
cam0@0 {
phandle = <0xe8>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x6500>;
};
};
id_enable {
phandle = <0x115>;
pins_cmd_dat {
input-enable;
bias-pull-up = <0x65>;
slew-rate = <0x00>;
pinmux = <0x1800>;
};
};
c1_low {
phandle = <0xfe>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1500>;
};
};
c1_high {
phandle = <0x100>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x1500>;
output-high;
};
};
cam1@3 {
phandle = <0xef>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x6200>;
output-high;
};
};
aw87339_r_gpio_init {
phandle = <0x118>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x4500>;
};
};
uart0_rx_set@gpio95 {
phandle = <0xcd>;
pins_cmd_dat {
pinmux = <0x5f01>;
};
};
aud_pins_smartpa_off {
phandle = <0xd7>;
pins_cmd0_dat {
pinmux = <0xae00>;
};
};
aud_dat_mosi_off {
phandle = <0xd3>;
pins_cmd1_dat {
pinmux = <0x8a00>;
};
pins_cmd2_dat {
pinmux = <0x8b00>;
};
};
gpiokey_init {
phandle = <0x112>;
pins_cmd_dat {
input-enable;
bias-pull-up = <0x00>;
slew-rate = <0x00>;
pinmux = <0x200>;
};
};
cam1@1 {
phandle = <0xed>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x6600>;
output-high;
};
};
id_init {
phandle = <0x114>;
pins_cmd_dat {
input-enable;
bias-pull-up = <0x65>;
slew-rate = <0x00>;
pinmux = <0x1800>;
};
};
camera_pins_cam0_mclk_6ma {
phandle = <0xf3>;
pins_cmd_dat {
pinmux = <0x6301>;
drive-strength = <0x02>;
};
};
uart0_rx_clear@gpio95 {
phandle = <0xce>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x5f00>;
output-high;
};
};
gpslna@1 {
phandle = <0xe1>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x9b00>;
output-high;
};
};
aw87339_r_default {
phandle = <0x117>;
};
irtx_gpio_led_set@gpio90 {
phandle = <0xe6>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x5a01>;
output-high;
};
};
u3_sw_sel2 {
phandle = <0x106>;
pins_cmd_dat {
slew-rate = <0x01>;
pinmux = <0x1c00>;
output-high;
};
};
aud_clk_mosi_off {
phandle = <0xd1>;
pins_cmd0_dat {
pinmux = <0x8800>;
};
};
extamp_pulllow {
phandle = <0xde>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x4500>;
};
};
aw87339_l_default {
phandle = <0x119>;
};
vow_clk_miso_on {
phandle = <0xdc>;
pins_cmd3_dat {
pinmux = <0x8f04>;
};
};
c2_low {
phandle = <0x102>;
pins_cmd_dat {
output-low;
slew-rate = <0x01>;
pinmux = <0x1600>;
};
};
};
md_ccif2@1023d000 {
reg = <0x00 0x1023d000 0x00 0x1000>;
compatible = "mediatek,md_ccif2";
};
mt_soc_dl1_pcm@11220000 {
pinctrl-6 = <0xd7>;
pinctrl-8 = <0xd9>;
phandle = <0xa2>;
reg = <0x00 0x11220000 0x00 0x1000>;
status = "okay";
pinctrl-1 = <0xd2>;
pinctrl-11 = <0xdc>;
compatible = "mediatek,mt_soc_pcm_dl1";
pinctrl-3 = <0xd4>;
pinctrl-13 = <0xde>;
pinctrl-5 = <0xd6>;
pinctrl-7 = <0xd8>;
clocks = <0x3d 0x09 0x3d 0x03 0x3d 0x02 0x3d 0x04 0x3d 0x0e 0x3d 0x08 0x3d 0x07 0x3d 0x05 0x3d 0x06 0x3d 0x01 0x2e 0x08 0x15 0x30 0x15 0x38 0x42 0x0c 0x42 0x0d 0x42 0x31 0x42 0x14 0x42 0x49 0x42 0x15 0x42 0x4d 0x42 0x1f 0x42 0x4c 0x42 0x20 0x42 0x50 0x2c>;
interrupts = <0x00 0xa1 0x08>;
pinctrl-9 = <0xda>;
clock-names = "aud_afe_clk\0aud_dac_clk\0aud_dac_predis_clk\0aud_adc_clk\0aud_adc_adda6_clk\0aud_apll22m_clk\0aud_apll24m_clk\0aud_apll1_tuner_clk\0aud_apll2_tuner_clk\0aud_tml_clk\0scp_sys_audio\0aud_infra_clk\0mtkaif_26m_clk\0top_mux_audio\0top_mux_audio_int\0top_syspll_d2_d4\0top_mux_aud_1\0top_apll1_ck\0top_mux_aud_2\0top_apll2_ck\0top_mux_aud_eng1\0top_apll1_d8\0top_mux_aud_eng2\0top_apll2_d8\0top_clk26m_clk";
pinctrl-0 = <0xd1>;
pinctrl-10 = <0xdb>;
pinctrl-2 = <0xd3>;
pinctrl-12 = <0xdd>;
pinctrl-names = "aud_clk_mosi_off\0aud_clk_mosi_on\0aud_dat_mosi_off\0aud_dat_mosi_on\0aud_dat_miso_off\0aud_dat_miso_on\0aud_smartpa_off\0aud_smartpa_on\0vow_dat_miso_off\0vow_dat_miso_on\0vow_clk_miso_off\0vow_clk_miso_on\0extamp-pullhigh\0extamp-pulllow";
pinctrl-4 = <0xd5>;
};
mp0_cpucfg@0c530000 {
reg = <0x00 0xc530000 0x00 0x1000>;
compatible = "mediatek,mp0_cpucfg";
};
ipu1@19280000 {
phandle = <0x4c>;
reg = <0x00 0x19280000 0x00 0x1000>;
compatible = "mediatek,ipu1\0syscon";
#clock-cells = <0x01>;
interrupts = <0x00 0x125 0x08>;
};
mt_soc_mrgrx_awb_pcm {
compatible = "mediatek,mt_soc_pcm_mrgrx_awb";
};
interrupt-controller@0c000000 {
interrupt-controller;
phandle = <0x11>;
reg = <0x00 0xc000000 0x00 0x40000 0x00 0xc100000 0x00 0x200000 0x00 0xc530a80 0x00 0x50>;
#interrupt-cells = <0x03>;
compatible = "arm,gic-v3";
interrupt-parent = <0x11>;
#size-cells = <0x02>;
interrupts = <0x01 0x09 0x04>;
#redistributor-regions = <0x01>;
#address-cells = <0x02>;
};
mt_soc_fm_i2s_awb_pcm {
compatible = "mediatek,mt_soc_pcm_fm_i2s_awb";
};
modem_topsm@87010000 {
reg = <0x00 0x87010000 0x00 0x1000>;
compatible = "mediatek,modem_topsm";
};
rt-pd-manager {
compatible = "mediatek,rt-pd-manager";
};
apcldmamisc@1021b800 {
reg = <0x00 0x1021b800 0x00 0x1000>;
compatible = "mediatek,apcldmamisc";
interrupts = <0x00 0xad 0x04>;
};
mt_soc_codec_dummy_name {
compatible = "mediatek,mt_soc_codec_dummy";
};
gpio {
GPIO_SIM2_SIO = <0x1b 0x23 0x00>;
phandle = <0x54>;
compatible = "mediatek,gpio_usage_mapping";
GPIO_SIM1_SIO = <0x1b 0x28 0x00>;
GPIO_SIM1_HOT_PLUG = <0x1b 0x2f 0x00>;
GPIO_SIM1_SCLK = <0x1b 0x26 0x00>;
GPIO_SIM1_SRST = <0x1b 0x27 0x00>;
GPIO_SIM2_SCLK = <0x1b 0x25 0x00>;
GPIO_SIM2_SRST = <0x1b 0x24 0x00>;
};
pericfg@10003000 {
reg = <0x00 0x10003000 0x00 0x1000>;
compatible = "mediatek,pericfg";
};
bsi_3g@87070000 {
reg = <0x00 0x87070000 0x00 0x1000>;
compatible = "mediatek,bsi_3g";
};
ap_dma@11000000 {
reg = <0x00 0x11000000 0x00 0x1000>;
compatible = "mediatek,ap_dma";
interrupts = <0x00 0x5e 0x08>;
};
seninf2@1a041000 {
reg = <0x00 0x1a041000 0x00 0x1000>;
compatible = "mediatek,seninf2";
};
hsce@87220000 {
reg = <0x00 0x87220000 0x00 0x1000>;
compatible = "mediatek,hsce";
};
toprgu@10007000 {
reg = <0x00 0x10007000 0x00 0x1000>;
compatible = "mediatek,toprgu";
interrupts = <0x00 0x8e 0x00>;
};
pwrap_mpu@1000d000 {
reg = <0x00 0x1000d000 0x00 0x1000>;
compatible = "mediatek,pwrap_mpu";
};
l2misc@850c0000 {
reg = <0x00 0x850c0000 0x00 0x1000>;
compatible = "mediatek,l2misc";
};
md_gpt@80030000 {
reg = <0x00 0x80030000 0x00 0x1000>;
compatible = "mediatek,md_gpt";
};
camsv5@1a054000 {
reg = <0x00 0x1a054000 0x00 0x1000>;
compatible = "mediatek,camsv5";
};
vpu_core0@0x19100000 {
reg = <0x00 0x19100000 0x00 0x94000>;
compatible = "mediatek,vpu_core0";
bin-phy-addr = <0x9d5f0000>;
clocks = <0x42 0x24 0x42 0x25 0x42 0x26 0x42 0x27 0x4b 0x01 0x4b 0x02 0x4b 0x03 0x4c 0x01 0x4c 0x02 0x4c 0x03 0x4d 0x01 0x4d 0x07 0x4d 0x08 0x4d 0x09 0x4d 0x0a 0x4d 0x0b 0x4d 0x0c 0x4d 0x0d 0x4d 0x0e 0x4d 0x0f 0x4d 0x01 0x4d 0x02 0x4d 0x03 0x4d 0x04 0x4d 0x05 0x4d 0x06 0x42 0x6f 0x42 0x70 0x42 0x3d 0x42 0x2d 0x42 0x40 0x42 0x30 0x42 0x43 0x42 0x34 0x2f 0x0a 0x2f 0x07 0x2f 0x05 0x2f 0x04 0x2f 0x01 0x2e 0x03 0x2e 0x0e 0x2e 0x0f 0x2e 0x10 0x2e 0x11 0x2e 0x12>;
interrupts = <0x00 0x124 0x08>;
clock-names = "clk_top_dsp_sel\0clk_top_dsp1_sel\0clk_top_dsp2_sel\0clk_top_ipu_if_sel\0clk_ipu_core0_jtag_cg\0clk_ipu_core0_axi_m_cg\0clk_ipu_core0_ipu_cg\0clk_ipu_core1_jtag_cg\0clk_ipu_core1_axi_m_cg\0clk_ipu_core1_ipu_cg\0clk_ipu_adl_cabgen\0clk_ipu_conn_dap_rx_cg\0clk_ipu_conn_apb2axi_cg\0clk_ipu_conn_apb2ahb_cg\0clk_ipu_conn_ipu_cab1to2\0clk_ipu_conn_ipu1_cab1to2\0clk_ipu_conn_ipu2_cab1to2\0clk_ipu_conn_cab3to3\0clk_ipu_conn_cab2to1\0clk_ipu_conn_cab3to1_slice\0clk_ipu_conn_ipu_cg\0clk_ipu_conn_ahb_cg\0clk_ipu_conn_axi_cg\0clk_ipu_conn_isp_cg\0clk_ipu_conn_cam_adl_cg\0clk_ipu_conn_img_adl_cg\0clk_top_mmpll_d6\0clk_top_mmpll_d7\0clk_top_univpll_d3\0clk_top_syspll_d3\0clk_top_univpll_d2_d2\0clk_top_syspll_d2_d2\0clk_top_univpll_d3_d2\0clk_top_syspll_d3_d2\0clk_mmsys_gals_ipu2mm\0clk_mmsys_gals_ipu12mm\0clk_mmsys_gals_comm1\0clk_mmsys_gals_comm0\0clk_mmsys_smi_common\0mtcmos_dis\0mtcmos_vpu_top\0mtcmos_vpu_core0_dormant\0mtcmos_vpu_core0_shutdown\0mtcmos_vpu_core1_dormant\0mtcmos_vpu_core1_shutdown";
bin-size = <0x2a10000>;
};
md_uart0@80010000 {
reg = <0x00 0x80010000 0x00 0x1000>;
compatible = "mediatek,md_uart0";
};
infracfg@1020e000 {
reg = <0x00 0x1020e000 0x00 0x1000>;
compatible = "mediatek,infracfg";
};
txupc@876b0000 {
reg = <0x00 0x876b0000 0x00 0x1000>;
compatible = "mediatek,txupc";
};
mdinfra_mbist_config@80350000 {
reg = <0x00 0x80350000 0x00 0x1000>;
compatible = "mediatek,mdinfra_mbist_config";
};
intpol-controller@0c530620 {
interrupt-controller;
phandle = <0x01>;
reg = <0x00 0xc530a80 0x00 0x50>;
#interrupt-cells = <0x03>;
compatible = "mediatek,mt6771-sysirq\0mediatek,mt6577-sysirq";
interrupt-parent = <0x11>;
};
irq_nfc {
phandle = <0xc4>;
compatible = "mediatek,irq_nfc-eint";
};
afc_2g@83090000 {
reg = <0x00 0x83090000 0x00 0x1000>;
compatible = "mediatek,afc_2g";
};
dvfsrc_top@10012000 {
reg = <0x00 0x10012000 0x00 0x1000 0x00 0x11bb80 0x00 0x80>;
compatible = "mediatek,dvfsrc_top";
};
dip2@15023000 {
reg = <0x00 0x15023000 0x00 0x1000>;
compatible = "mediatek,dip2";
};
scp_spi1@105d0000 {
reg = <0x00 0x105d0000 0x00 0x1000>;
compatible = "mediatek,scp_spi1";
};
txcrp@87690000 {
reg = <0x00 0x87690000 0x00 0x1000>;
compatible = "mediatek,txcrp";
};
avc_mv@16024000 {
reg = <0x00 0x16024000 0x00 0x1000>;
compatible = "mediatek,avc_mv";
};
vld@16021000 {
reg = <0x00 0x16021000 0x00 0x1000>;
compatible = "mediatek,vld";
};
i2c6@11005000 {
reg = <0x00 0x11005000 0x00 0x1000>;
compatible = "mediatek,i2c6";
interrupts = <0x00 0x57 0x08>;
};
ufs_mphy@11fa0000 {
reg = <0x00 0x11fa0000 0x00 0xc000>;
compatible = "mediatek,ufs_mphy";
};
rake_2@87840000 {
reg = <0x00 0x87840000 0x00 0x1000>;
compatible = "mediatek,rake_2";
};
mt_soc_pcm_voice_scp {
compatible = "mediatek,mt_soc_pcm_voice_scp";
};
disp_color0@1400e000 {
phandle = <0x3a>;
reg = <0x00 0x1400e000 0x00 0x1000>;
compatible = "mediatek,disp_color0";
clocks = <0x2f 0x1a>;
interrupts = <0x00 0xe7 0x08>;
clock-names = "MDP_COLOR";
};
mcucfg_mp0_counter@0c530000 {
reg = <0x00 0xc530000 0x00 0x2000>;
compatible = "mediatek,mcucfg_mp0_counter";
};
hseq@87210000 {
reg = <0x00 0x87210000 0x00 0x1000>;
compatible = "mediatek,hseq";
};
fhctl@1000ce00 {
reg = <0x00 0x1000ce00 0x00 0x1000>;
compatible = "mediatek,fhctl";
};
pf_bsi_apb1@80200000 {
reg = <0x00 0x80200000 0x00 0x1000>;
compatible = "mediatek,pf_bsi_apb1";
};
apcldmamisc_ao@10014800 {
reg = <0x00 0x10014800 0x00 0x1000>;
compatible = "mediatek,apcldmamisc_ao";
};
usb_c_pinctrl {
phandle = <0xc8>;
};
memory-ssmr-features {
sdsp-tee-sharedmem-size = <0x00 0x1000000>;
svp-size = <0x00 0x10000000>;
ta-stack-heap-size = <0x00 0x6000000>;
phandle = <0xb0>;
compatible = "mediatek,memory-ssmr-features";
tui-size = <0x00 0x4000000>;
2d_fr-size = <0x00 0x8000000>;
prot-sharedmem-size = <0x00 0x8000000>;
wfd-size = <0x00 0x4000000>;
iris-recognition-size = <0x00 0x10000000>;
ta-elf-size = <0x00 0x1000000>;
sdsp-firmware-size = <0x00 0x1000000>;
};
ap_ccif2@1023c000 {
reg = <0x00 0x1023c000 0x00 0x1000>;
compatible = "mediatek,ap_ccif2";
interrupts = <0x00 0x9c 0x08>;
};
mipi0_bsispi@80205000 {
reg = <0x00 0x80205000 0x00 0x1000>;
compatible = "mediatek,mipi0_bsispi";
};
irtx_pwm {
phandle = <0x9e>;
pwm_data_invert = <0x00>;
status = "okay";
pinctrl-1 = <0xe6>;
compatible = "mediatek,irtx-pwm";
pwm_ch = <0x00>;
pinctrl-0 = <0xe5>;
pinctrl-names = "irtx_gpio_led_default\0irtx_gpio_led_set";
};
md2_abb_mixedsys@8020c000 {
reg = <0x00 0x8020c000 0x00 0x1000>;
compatible = "mediatek,md2_abb_mixedsys";
};
cam3@1a006000 {
reg = <0x00 0x1a006000 0x00 0x2000>;
compatible = "mediatek,cam3";
interrupts = <0x00 0xff 0x08>;
};
i2c@11016000 {
phandle = <0x61>;
mediatek,use-open-drain;
reg = <0x00 0x11016000 0x00 0x1000 0x00 0x11000500 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x45 0x15 0x2b 0x15 0x46>;
interrupts = <0x00 0x56 0x08>;
id = <0x0b>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
clock-div = <0x05>;
};
disp_rsz@1401a000 {
reg = <0x00 0x1401a000 0x00 0x1000>;
compatible = "mediatek,disp_rsz";
interrupts = <0x00 0xf1 0x08>;
};
rake_0@87820000 {
reg = <0x00 0x87820000 0x00 0x1000>;
compatible = "mediatek,rake_0";
};
mdcldmaout@1021c400 {
reg = <0x00 0x1021c400 0x00 0x1000>;
compatible = "mediatek,mdcldmaout";
};
ccu@1a0a0000 {
reg = <0x00 0x1a0a1000 0x00 0x1000>;
compatible = "mediatek,ccu";
clocks = <0x4a 0x09 0x2f 0x06 0x2e 0x09>;
interrupts = <0x00 0x108 0x08>;
clock-names = "CCU_CLK_CAM_CCU\0CCU_CLK_MMSYS_CCU\0CAM_PWR";
};
scp@10500000 {
scp_sramSize = <0x80000>;
phandle = <0x92>;
reg = <0x00 0x10500000 0x00 0x80000 0x00 0x105c0000 0x00 0x3000 0x00 0x105c4000 0x00 0x1000 0x00 0x105d4000 0x00 0x6000>;
core_1 = "enable";
status = <0x6f6b6179>;
compatible = "mediatek,scp";
interrupts = <0x00 0xae 0x04>;
};
md_soe@80310000 {
reg = <0x00 0x80310000 0x00 0x1000>;
compatible = "mediatek,md_soe";
interrupts = <0x00 0x11e 0x08>;
};
dbg@87880000 {
reg = <0x00 0x87880000 0x00 0x1000>;
compatible = "mediatek,dbg";
};
spi5@11019000 {
mediatek,pad-select = <0x00>;
phandle = <0x9d>;
reg = <0x00 0x11019000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x4d>;
interrupts = <0x00 0x87 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
md_pll_mixedsys@80140000 {
reg = <0x00 0x80140000 0x00 0x1000>;
compatible = "mediatek,md_pll_mixedsys";
};
l2ulsbdma@85000000 {
reg = <0x00 0x85000000 0x00 0x1000>;
compatible = "mediatek,l2ulsbdma";
};
mdperi_mbist_config@801a0000 {
reg = <0x00 0x801a0000 0x00 0x1000>;
compatible = "mediatek,mdperi_mbist_config";
};
mc@16022000 {
reg = <0x00 0x16022000 0x00 0x1000>;
compatible = "mediatek,mc";
};
sys_timer@10017000 {
reg = <0x00 0x10017000 0x00 0x1000>;
compatible = "mediatek,sys_timer";
interrupts = <0x00 0xca 0x04>;
reg-names = "sys_timer_base";
};
dpe@15028000 {
reg = <0x00 0x15028000 0x00 0x1000>;
compatible = "mediatek,dpe";
clocks = <0x49 0x06>;
interrupts = <0x00 0x10e 0x08>;
clock-names = "DPE_CG_IMG_DPE";
};
mipi_tx1@10216000 {
reg = <0x00 0x10216000 0x00 0x1000>;
compatible = "mediatek,mipi_tx1";
};
i2c@1401e000 {
reg = <0x00 0x1401e000 0x00 0x1000>;
compatible = "mediatek,i2c";
};
emi@10219000 {
emi_info,rank_size = <0x10 0x20>;
emi_info,rk_num = <0x02>;
emi_info,dram_type = <0x03>;
reg = <0x00 0x10219000 0x00 0x1000 0x00 0x10226000 0x00 0x1000 0x00 0x1022d000 0x00 0x1000 0x00 0x10235000 0x00 0x1000>;
compatible = "mediatek,emi";
interrupts = <0x00 0x93 0x08 0x00 0x94 0x04 0x00 0x9b 0x04>;
emi_info,ch_num = <0x02>;
};
gic@1023a000 {
reg = <0x00 0x1023a000 0x00 0x1000>;
compatible = "mediatek,gic";
};
mmdvfs_pmqos {
img_step0 = <0x20d 0x01 0x02 0x05>;
vdec_freq = "mm_step0\0mm_step1";
mdp_freq = "mm_step0\0mm_step1";
cam_freq = "cam_step0\0cam_step1";
compatible = "mediatek,mmdvfs_pmqos";
cam_step0 = <0x222 0x01 0x01 0x03>;
mm_step1 = <0x138 0x01 0x00 0x07>;
venc_freq = "mm_step0\0mm_step1";
disp_freq = "mm_step0\0mm_step1";
img_step1 = <0x16c 0x01 0x02 0x04>;
clocks = <0x42 0x02 0x42 0x03 0x42 0x23 0x42 0x2c 0x42 0x2d 0x42 0x6f 0x42 0x70 0x42 0x40>;
vopp_steps = <0x00 0x01>;
img_freq = "img_step0\0img_step1";
clock-names = "mmdvfs_clk_mux_top_mm_sel\0mmdvfs_clk_mux_top_cam_sel\0mmdvfs_clk_mux_top_img_sel\0mmdvfs_clk_syspll_d2_ck\0mmdvfs_clk_syspll_d3_ck\0mmdvfs_clk_mmpll_d6_ck\0mmdvfs_clk_mmpll_d7_ck\0mmdvfs_clk_univpll_d2_d2_ck";
cam_step1 = <0x16c 0x01 0x01 0x04>;
mm_step0 = <0x1c2 0x01 0x00 0x06>;
};
seninf1@1a040000 {
reg = <0x00 0x1a040000 0x00 0x1000>;
compatible = "mediatek,seninf1";
};
nfc {
gpio-rst-std = <0x1b 0x13 0x00>;
gpio-irq-std = <0x1b 0x14 0x00>;
phandle = <0xc3>;
gpio-rst = <0x13>;
compatible = "mediatek,nfc-gpio-v2";
gpio-irq = <0x14>;
};
pp_vmmu@16029000 {
reg = <0x00 0x16029000 0x00 0x1000>;
compatible = "mediatek,pp_vmmu";
};
therm_ctrl@1100b000 {
reg = <0x00 0x1100b000 0x00 0x1000>;
compatible = "mediatek,therm_ctrl";
clocks = <0x15 0x0a>;
interrupts = <0x00 0x4c 0x08>;
clock-names = "therm-main";
};
camsv4@1a053000 {
reg = <0x00 0x1a053000 0x00 0x1000>;
compatible = "mediatek,camsv4";
interrupts = <0x00 0x105 0x08>;
};
sys_cirq@10204000 {
reg = <0x00 0x10204000 0x00 0x1000>;
compatible = "mediatek,sys_cirq";
mediatek,spi_start_offset = <0x48>;
mediatek,cirq_num = <0xe7>;
interrupts = <0x00 0x12f 0x08>;
};
pwm@11006000 {
reg = <0x00 0x11006000 0x00 0x1000>;
compatible = "mediatek,pwm";
clocks = <0x15 0x10 0x15 0x11 0x15 0x12 0x15 0x13 0x15 0x0f 0x15 0x14>;
interrupts = <0x00 0x4b 0x08>;
clock-names = "PWM1-main\0PWM2-main\0PWM3-main\0PWM4-main\0PWM-HCLK-main\0PWM-main";
};
dsi1@1401f000 {
reg = <0x00 0x1401f000 0x00 0x1000>;
compatible = "mediatek,dsi1";
};
mt_soc_voice_md1 {
compatible = "mediatek,mt_soc_pcm_voice_md1";
};
mipi_rx_ana_csi2b@11c85000 {
reg = <0x00 0x11c85000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi2b";
};
i2c@11008000 {
phandle = <0x5a>;
mediatek,use-open-drain;
reg = <0x00 0x11008000 0x00 0x1000 0x00 0x11000100 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
ccu-ch-offset = <0x200>;
clocks = <0x15 0x0c 0x15 0x2b 0x15 0x48>;
interrupts = <0x00 0x52 0x08>;
id = <0x04>;
ch_offset_default = <0x100>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
clock-div = <0x05>;
camera_main@1a {
phandle = <0x12d>;
reg = <0x1a>;
status = "okay";
compatible = "mediatek,camera_main";
};
camera_main_af@72 {
phandle = <0x12e>;
reg = <0x72>;
status = "okay";
compatible = "mediatek,camera_main_af";
};
camera_main_eeprom@50 {
phandle = <0x12f>;
reg = <0x50>;
status = "okay";
compatible = "mediatek,camera_main_eeprom";
};
};
ipu_conn@19000000 {
phandle = <0x4d>;
reg = <0x00 0x19000000 0x00 0x1000>;
compatible = "mediatek,ipu_conn\0syscon";
#clock-cells = <0x01>;
};
disp_ccorr0@1400f000 {
reg = <0x00 0x1400f000 0x00 0x1000>;
compatible = "mediatek,disp_ccorr0";
interrupts = <0x00 0xe8 0x08>;
};
hspasys_3_mbist@876e0000 {
reg = <0x00 0x876e0000 0x00 0x1000>;
compatible = "mediatek,hspasys_3_mbist";
};
alc@60000000 {
reg = <0x00 0x60000000 0x00 0x1000>;
compatible = "mediatek,alc";
};
share_d1@82ca0000 {
reg = <0x00 0x82ca0000 0x00 0x1000>;
compatible = "mediatek,share_d1";
};
i2c_common {
idvfs = [01];
ver = [02];
phandle = <0x55>;
check_max_freq = [01];
compatible = "mediatek,i2c_common";
set_dt_div = [01];
set_ltiming = [01];
dma_support = [02];
ext_time_config = [18 01];
cnt_constraint = [01];
};
mt_soc_hp_impedance_pcm {
compatible = "mediatek,mt_soc_pcm_hp_impedance";
};
dip1@15022000 {
reg = <0x00 0x15022000 0x00 0x6000>;
compatible = "mediatek,dip1";
interrupts = <0x00 0x10c 0x08>;
};
disp_rdma1@1400c000 {
reg = <0x00 0x1400c000 0x00 0x1000>;
compatible = "mediatek,disp_rdma1";
interrupts = <0x00 0xe5 0x08>;
};
clocks {
clk32k {
phandle = <0x2b>;
compatible = "fixed-clock";
clock-frequency = <0x7d00>;
#clock-cells = <0x00>;
};
clk26m {
phandle = <0x2c>;
compatible = "fixed-clock";
clock-frequency = <0x18cba80>;
#clock-cells = <0x00>;
};
clk_null {
phandle = <0x53>;
compatible = "fixed-clock";
clock-frequency = <0x00>;
#clock-cells = <0x00>;
};
};
mtkfb@0 {
phandle = <0xa7>;
compatible = "mediatek,mtkfb";
};
disp_wdma0@1400d000 {
reg = <0x00 0x1400d000 0x00 0x1000>;
compatible = "mediatek,disp_wdma0";
interrupts = <0x00 0xe6 0x08>;
};
msdc1_top@11e10000 {
reg = <0x00 0x11e10000 0x00 0x1000>;
compatible = "mediatek,msdc1_top";
};
pwrap@1000d000 {
phandle = <0x2d>;
reg = <0x00 0x1000d000 0x00 0x1000>;
compatible = "mediatek,pwrap";
clocks = <0x2c 0x2c>;
interrupts = <0x00 0xb9 0x04>;
reg-names = "pwrap";
clock-names = "spi\0wrap";
mt6358-pmic {
interrupt-controller;
mediatek,pmic-irqs = <0x00 0x00 0x01 0x00 0x02 0x00 0x03 0x00 0x04 0x00 0x05 0x00 0x06 0x00 0x07 0x00 0x08 0x00 0x09 0x00 0x10 0x01 0x11 0x01 0x12 0x01 0x13 0x01 0x14 0x01 0x15 0x01 0x16 0x01 0x17 0x01 0x18 0x01 0x19 0x01 0x1a 0x01 0x1b 0x01 0x1c 0x01 0x1d 0x01 0x1e 0x01 0x1f 0x01 0x20 0x01 0x21 0x01 0x22 0x01 0x23 0x01 0x24 0x01 0x25 0x01 0x26 0x01 0x27 0x01 0x28 0x01 0x29 0x01 0x2a 0x01 0x2b 0x01 0x2c 0x01 0x2d 0x01 0x2e 0x01 0x30 0x02 0x31 0x02 0x32 0x02 0x33 0x02 0x34 0x02 0x35 0x02 0x36 0x02 0x37 0x02 0x40 0x03 0x50 0x04 0x51 0x04 0x52 0x04 0x53 0x04 0x54 0x04 0x55 0x04 0x56 0x04 0x57 0x04 0x58 0x04 0x59 0x04 0x5a 0x04 0x5b 0x04 0x5c 0x04 0x60 0x04 0x61 0x04 0x62 0x04 0x63 0x04 0x64 0x04 0x70 0x05 0x71 0x05 0x72 0x05 0x73 0x05 0x74 0x05 0x75 0x05 0x76 0x05 0x77 0x05 0x80 0x06 0x85 0x06 0x86 0x06 0x87 0x06 0x90 0x07>;
phandle = <0x63>;
interrupt-names = "vproc11_oc\0vproc12_oc\0vcore_oc\0vgpu_oc\0vmodem_oc\0vdram1_oc\0vs1_oc\0vs2_oc\0vpa_oc\0vcore_preoc\0vfe28_oc\0vxo22_oc\0vrf18_oc\0vrf12_oc\0vefuse_oc\0vcn33_oc\0vcn28_oc\0vcn18_oc\0vcama1_oc\0vcama2_oc\0vcamd_oc\0vcamio_oc\0vldo28_oc\0va12_oc\0vaux18_oc\0vaud28_oc\0vio28_oc\0vio18_oc\0vsram_proc11_oc\0vsram_proc12_oc\0vsram_others_oc\0vsram_gpu_oc\0vdram2_oc\0vmc_oc\0vmch_oc\0vemc_oc\0vsim1_oc\0vsim2_oc\0vibr_oc\0vusb_oc\0vbif28_oc\0pwrkey\0homekey\0pwrkey_r\0homekey_r\0ni_lbat_int\0chrdet\0chrdet_edge\0vcdt_hv_det\0rtc\0fg_bat0_h\0fg_bat0_l\0fg_cur_h\0fg_cur_l\0fg_zcv\0fg_bat1_h\0fg_bat1_l\0fg_n_charge_l\0fg_iavg_h\0fg_iavg_l\0fg_time_h\0fg_discharge\0fg_charge\0baton_lv\0baton_ht\0baton_bat_in\0baton_bat_out\0bif\0bat_h\0bat_l\0bat2_h\0bat2_l\0bat_temp_h\0bat_temp_l\0auxadc_imp\0nag_c_dltv\0audio\0accdet\0accdet_eint0\0accdet_eint1\0spi_cmd_alert";
status = "okay";
#interrupt-cells = <0x02>;
compatible = "mediatek,mt6358-pmic";
mediatek,num-pmic-irqs = <0x91>;
interrupt-parent = <0x1b>;
interrupts = <0xb6 0x04 0xbe 0x00>;
mt-pmic {
phandle = <0x64>;
interrupt-names = "pwrkey\0pwrkey_r\0homekey\0homekey_r\0bat_h\0bat_l\0fg_cur_h\0fg_cur_l";
compatible = "mediatek,mt-pmic";
interrupts = <0x30 0x04 0x32 0x04 0x31 0x04 0x33 0x04 0x70 0x04 0x71 0x04 0x52 0x04 0x53 0x04>;
};
mt6358_misc {
dcxo-switch;
phandle = <0x8f>;
apply-lpsd-solution;
compatible = "mediatek,mt6358-misc";
base = <0x580>;
};
mt635x-auxadc {
phandle = <0x65>;
compatible = "mediatek,mt6358-auxadc";
#io-channel-cells = <0x01>;
dcxo_volt {
resistance-ratio = <0x03 0x02>;
channel = <0x0a>;
};
bat_temp {
resistance-ratio = <0x02 0x01>;
channel = <0x03>;
};
vbif {
resistance-ratio = <0x02 0x01>;
channel = <0x0e>;
};
chip_temp {
channel = <0x05>;
};
accdet {
channel = <0x09>;
};
vcdt {
channel = <0x02>;
};
vcore_temp {
channel = <0x06>;
};
batadc {
resistance-ratio = <0x03 0x01>;
channel = <0x00>;
avg-num = <0x80>;
};
vgpu_temp {
channel = <0x08>;
};
vproc_temp {
channel = <0x07>;
};
dcxo_temp {
channel = <0x0d>;
avg-num = <0x10>;
};
hpofs_cal {
channel = <0x0c>;
avg-num = <0x100>;
};
tsx_temp {
channel = <0x0b>;
avg-num = <0x80>;
};
};
mt6358_rtc {
phandle = <0x8e>;
apply-lpsd-solution;
interrupt-names = "rtc";
compatible = "mediatek,mt6358-rtc";
interrupts = <0x40 0x00>;
base = <0x580>;
};
mt6358regulator {
phandle = <0x66>;
compatible = "mediatek,mt6358-regulator";
buck_vmodem {
phandle = <0x6e>;
regulator-name = "vmodem";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0x384>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vcn28 {
phandle = <0x7b>;
compatible = "regulator-fixed";
regulator-name = "vcn28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2ab980>;
};
ldo_vcn18 {
phandle = <0x78>;
compatible = "regulator-fixed";
regulator-name = "vcn18";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vefuse {
phandle = <0x7f>;
regulator-name = "vefuse";
regulator-min-microvolt = <0x19f0a0>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x1cfde0>;
};
ldo_vldo28 {
regulator-default-on = <0x01>;
phandle = <0x8a>;
status = "okay";
regulator-name = "vldo28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2dc6c0>;
};
ldo_vsram_proc12 {
phandle = <0x82>;
regulator-name = "vsram_proc12";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xf0>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vrf18 {
phandle = <0x86>;
compatible = "regulator-fixed";
regulator-name = "vrf18";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x78>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vemc {
phandle = <0x14>;
regulator-name = "vemc";
regulator-min-microvolt = <0x2c4020>;
regulator-enable-ramp-delay = <0x3c>;
regulator-max-microvolt = <0x325aa0>;
};
buck_vproc12 {
phandle = <0x6b>;
regulator-name = "vproc12";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xc8>;
regulator-max-microvolt = <0x13bdb6>;
};
buck_vs2 {
phandle = <0x6d>;
regulator-name = "vs2";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0x00>;
regulator-max-microvolt = <0x1fda4c>;
};
ldo_vdram2 {
phandle = <0x70>;
regulator-name = "vdram2";
regulator-min-microvolt = <0x927c0>;
regulator-enable-ramp-delay = <0xce4>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vcama1 {
regulator-default-on = <0x01>;
phandle = <0x83>;
status = "okay";
regulator-name = "vcama1";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2dc6c0>;
};
ldo_vmch {
phandle = <0x1c>;
regulator-name = "vmch";
regulator-min-microvolt = <0x2c4020>;
regulator-enable-ramp-delay = <0x3c>;
regulator-max-microvolt = <0x325aa0>;
};
ldo_vcamio {
regulator-default-on = <0x01>;
phandle = <0x76>;
status = "okay";
compatible = "regulator-fixed";
regulator-name = "vcamio";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vaux18 {
phandle = <0x80>;
compatible = "regulator-fixed";
regulator-name = "vaux18";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vsram_others {
phandle = <0x7c>;
regulator-name = "vsram_others";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xf0>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vsim1 {
regulator-default-on = <0x01>;
phandle = <0x71>;
status = "okay";
regulator-name = "vsim1";
regulator-min-microvolt = <0x19f0a0>;
regulator-enable-ramp-delay = <0x21c>;
regulator-max-microvolt = <0x2f4d60>;
};
ldo_va12 {
phandle = <0x85>;
compatible = "regulator-fixed";
regulator-name = "va12";
regulator-min-microvolt = <0x124f80>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x124f80>;
};
buck_vgpu {
phandle = <0x6c>;
regulator-name = "vgpu";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xc8>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vrf12 {
phandle = <0x73>;
compatible = "regulator-fixed";
regulator-name = "vrf12";
regulator-min-microvolt = <0x124f80>;
regulator-enable-ramp-delay = <0x78>;
regulator-max-microvolt = <0x124f80>;
};
ldo_vibr {
phandle = <0x72>;
regulator-name = "vibr";
regulator-min-microvolt = <0x124f80>;
regulator-enable-ramp-delay = <0x3c>;
regulator-max-microvolt = <0x325aa0>;
};
buck_vcore {
phandle = <0x68>;
regulator-name = "vcore";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xc8>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vaud28 {
phandle = <0x8b>;
compatible = "regulator-fixed";
regulator-name = "vaud28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2ab980>;
};
ldo_vbif28 {
phandle = <0x81>;
compatible = "regulator-fixed";
regulator-name = "vbif28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2ab980>;
};
ldo_va09 {
phandle = <0x8d>;
compatible = "regulator-fixed";
regulator-name = "va09";
regulator-min-microvolt = <0xdbba0>;
regulator-enable-ramp-delay = <0x108>;
regulator-boot-on;
regulator-max-microvolt = <0xdbba0>;
};
ldo_vxo22 {
phandle = <0x7e>;
compatible = "regulator-fixed";
regulator-name = "vxo22";
regulator-min-microvolt = <0x2191c0>;
regulator-enable-ramp-delay = <0x78>;
regulator-max-microvolt = <0x2191c0>;
};
ldo_vsram_proc11 {
phandle = <0x7a>;
regulator-name = "vsram_proc11";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xf0>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vmc {
phandle = <0x1d>;
regulator-name = "vmc";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x3c>;
regulator-max-microvolt = <0x325aa0>;
};
ldo_vio28 {
phandle = <0x84>;
compatible = "regulator-fixed";
regulator-name = "vio28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2ab980>;
};
ldo_vcama2 {
regulator-default-on = <0x01>;
phandle = <0x89>;
status = "okay";
regulator-name = "vcama2";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2dc6c0>;
};
ldo_vcn33_wifi {
phandle = <0x88>;
regulator-name = "vcn33_wifi";
regulator-min-microvolt = <0x325aa0>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x3567e0>;
};
ldo_vio18 {
phandle = <0x74>;
compatible = "regulator-fixed";
regulator-name = "vio18";
regulator-min-microvolt = <0x1b7740>;
regulator-enable-ramp-delay = <0xa8c>;
regulator-max-microvolt = <0x1b7740>;
};
buck_vproc11 {
phandle = <0x6a>;
regulator-name = "vproc11";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xc8>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vfe28 {
phandle = <0x79>;
compatible = "regulator-fixed";
regulator-name = "vfe28";
regulator-min-microvolt = <0x2ab980>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2ab980>;
};
buck_vpa {
phandle = <0x69>;
regulator-name = "vpa";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xfa>;
regulator-max-microvolt = <0x37b1d0>;
};
ldo_vcn33_bt {
phandle = <0x87>;
regulator-name = "vcn33_bt";
regulator-min-microvolt = <0x325aa0>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x3567e0>;
};
buck_vdram1 {
phandle = <0x67>;
regulator-name = "vdram1";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0x00>;
regulator-max-microvolt = <0x1fda4c>;
};
buck_vs1 {
phandle = <0x6f>;
regulator-name = "vs1";
regulator-min-microvolt = <0xf4240>;
regulator-enable-ramp-delay = <0x00>;
regulator-max-microvolt = <0x277b6c>;
};
ldo_vcamd {
regulator-default-on = <0x01>;
phandle = <0x77>;
status = "okay";
regulator-name = "vcamd";
regulator-min-microvolt = <0xdbba0>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x1b7740>;
};
ldo_vsim2 {
regulator-default-on = <0x01>;
phandle = <0x8c>;
status = "okay";
regulator-name = "vsim2";
regulator-min-microvolt = <0x19f0a0>;
regulator-enable-ramp-delay = <0x21c>;
regulator-max-microvolt = <0x2f4d60>;
};
ldo_vsram_gpu {
phandle = <0x7d>;
regulator-name = "vsram_gpu";
regulator-min-microvolt = <0x7a120>;
regulator-enable-ramp-delay = <0xf0>;
regulator-max-microvolt = <0x13bdb6>;
};
ldo_vusb {
phandle = <0x75>;
regulator-name = "vusb";
regulator-min-microvolt = <0x2dc6c0>;
regulator-enable-ramp-delay = <0x10e>;
regulator-max-microvolt = <0x2f4d60>;
};
};
};
};
i2c@11005000 {
phandle = <0x5c>;
mediatek,use-open-drain;
reg = <0x00 0x11005000 0x00 0x1000 0x00 0x11000600 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x58 0x15 0x2b>;
interrupts = <0x00 0x57 0x08>;
id = <0x06>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
aw87339@59 {
reg = <0x59>;
status = "okay";
compatible = "awinic,aw87339_l";
pinctrl-0 = <0x119>;
pinctrl-names = "aw87339_default";
};
rt9465@4b {
rt,intr_gpio = <0x1b 0x09 0x00>;
reg = <0x4b>;
mt6306_en_pin = <0x01>;
interrupt-names = "wdtmri";
rt,en_gpio_num = <0xb3>;
status = "okay";
rt,intr_gpio_num = <0x09>;
en_wdt;
compatible = "richtek,rt9465";
charger_name = "secondary_chg";
ieoc = <0xaae60>;
en_st;
mivr = <0x44aa20>;
safety_timer = <0x0c>;
rt,en_gpio = <0x1b 0xb3 0x00>;
ichg = <0x16e360>;
cv = <0x456d70>;
};
aw87339@58 {
reg = <0x58>;
status = "okay";
pinctrl-1 = <0x118>;
compatible = "awinic,aw87339_r";
reset_gpio = <0x1b 0x45 0x00>;
pinctrl-0 = <0x117>;
pinctrl-names = "aw87339_default\0aw87339_gpio_init";
};
slave_charger@4b {
phandle = <0x132>;
reg = <0x4b>;
status = "okay";
compatible = "mediatek,slave_charger";
};
};
smi_larb0@14017000 {
phandle = <0x3f>;
reg = <0x00 0x14017000 0x00 0x1000>;
compatible = "mediatek,smi_larb0\0mediatek,smi_larb";
mediatek,smi-id = <0x00>;
clocks = <0x2e 0x03 0x2f 0x02>;
interrupts = <0x00 0xf0 0x08>;
clock-names = "mtcmos-mm\0mm-larb0";
};
scp_dma@105cd000 {
reg = <0x00 0x105cd000 0x00 0x1000>;
compatible = "mediatek,scp_dma";
};
cq_dma@10212000 {
reg = <0x00 0x10212000 0x00 0x80 0x00 0x10212080 0x00 0x80 0x00 0x10212100 0x00 0x80>;
compatible = "mediatek,mt-cqdma-v1";
nr_channel = <0x03>;
clocks = <0x15 0x4e>;
interrupts = <0x00 0x73 0x08 0x00 0x74 0x08 0x00 0x75 0x08>;
clock-names = "cqdma";
};
bus_dbg@10208000 {
reg = <0x00 0x10208000 0x00 0x1000>;
compatible = "mediatek,bus_dbg-v2";
interrupts = <0x00 0x90 0x08>;
};
eaf@1502d000 {
reg = <0x00 0x1502d000 0x00 0x1000>;
compatible = "mediatek,eaf";
};
aes_top0@10016000 {
reg = <0x00 0x10016000 0x00 0x1000>;
compatible = "mediatek,aes_top0";
};
dpi0@14015000 {
reg = <0x00 0x14015000 0x00 0x1000>;
compatible = "mediatek,dpi0";
interrupts = <0x00 0xed 0x08>;
};
devapc@10207000 {
reg = <0x00 0x10207000 0x00 0x1000 0x00 0x1000e000 0x00 0x1000>;
compatible = "mediatek,devapc";
clocks = <0x15 0x2d>;
interrupts = <0x00 0x91 0x08>;
clock-names = "devapc-infra-clock";
};
hspasys_4_confg@87870000 {
reg = <0x00 0x87870000 0x00 0x1000>;
compatible = "mediatek,hspasys_4_confg";
};
fcs@83050000 {
reg = <0x00 0x83050000 0x00 0x1000>;
compatible = "mediatek,fcs";
};
vdtop@16020000 {
reg = <0x00 0x16020000 0x00 0x1000>;
compatible = "mediatek,vdtop";
};
hspasys_1_mbist@87230000 {
reg = <0x00 0x87230000 0x00 0x1000>;
compatible = "mediatek,hspasys_1_mbist";
};
mfg_tb@13ffef00 {
reg = <0x00 0x13ffef00 0x00 0x1000>;
compatible = "mediatek,mfg_tb";
};
mdp_wrot1@14020000 {
reg = <0x00 0x14020000 0x00 0x1000>;
compatible = "mediatek,mdp_wrot1";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
modem_confg@87000000 {
reg = <0x00 0x87000000 0x00 0x1000>;
compatible = "mediatek,modem_confg";
};
md_peri_misc@80060000 {
reg = <0x00 0x80060000 0x00 0x1000>;
compatible = "mediatek,md_peri_misc";
};
mt_soc_i2s0_pcm {
compatible = "mediatek,mt_soc_pcm_dl1_i2s0";
};
flashlight_core {
phandle = <0xad>;
compatible = "mediatek,flashlight_core";
};
rsvd@10009000 {
reg = <0x00 0x10009000 0x00 0x1000>;
compatible = "mediatek,rsvd";
};
md_sdf_top@801b0000 {
reg = <0x00 0x801b0000 0x00 0x1000>;
compatible = "mediatek,md_sdf_top";
};
mt_soc_dummy_pcm {
compatible = "mediatek,mt_soc_pcm_dummy";
};
mt_soc_fm_i2s_pcm {
compatible = "mediatek,mt_soc_pcm_fm_i2s";
};
md1_sim1_hot_plug_eint {
dedicated = <0x01 0x00>;
phandle = <0xc6>;
status = "okay";
sockettype = <0x01 0x00>;
compatible = "mediatek,md1_sim1_hot_plug_eint-eint";
src_pin = <0x01 0x01>;
interrupts = <0x01 0x08>;
debounce = <0x01 0x186a0>;
};
wifi@180f0000 {
phandle = <0x94>;
reg = <0x00 0x180f0000 0x00 0x1100 0x00 0x10212180 0x00 0x6c 0x00 0x10001000 0x00 0x1000 0x00 0x180e0000 0x00 0x70>;
hardware-values = <0x788 0xa5800 0xa5800>;
compatible = "mediatek,wifi";
clocks = <0x15 0x4e>;
interrupts = <0x00 0x122 0x08 0x00 0x76 0x08>;
clock-names = "wifi-dma";
};
md_abm@80260000 {
reg = <0x00 0x80260000 0x00 0x1000>;
compatible = "mediatek,md_abm";
};
pwraphal@ {
mediatek,pwrap-regmap = <0x2d>;
phandle = <0x90>;
compatible = "mediatek,pwraph";
};
spi4@11018000 {
mediatek,pad-select = <0x00>;
phandle = <0x9c>;
reg = <0x00 0x11018000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x4c>;
interrupts = <0x00 0x86 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
md_pcm@80220000 {
reg = <0x00 0x80220000 0x00 0x1000>;
compatible = "mediatek,md_pcm";
};
flashlights_mt6370 {
decouple = <0x01>;
phandle = <0xae>;
compatible = "mediatek,flashlights_mt6370";
channel@1 {
type = <0x00>;
part = <0x00>;
ct = <0x00>;
};
};
mfb@1502e000 {
reg = <0x00 0x1502e000 0x00 0x1000>;
compatible = "mediatek,mfb";
clocks = <0x49 0x04>;
interrupts = <0x00 0x114 0x08>;
clock-names = "MFB_CLK_IMG_MFB";
};
rxbrp@87660000 {
reg = <0x00 0x87660000 0x00 0x1000>;
compatible = "mediatek,rxbrp";
};
topckgen@10000000 {
phandle = <0x42>;
reg = <0x00 0x10000000 0x00 0x1000>;
compatible = "mediatek,topckgen\0syscon";
#clock-cells = <0x01>;
};
tsf@1a0a1000 {
reg = <0x00 0x1a0a1000 0x00 0x1000>;
compatible = "mediatek,tsf";
clocks = <0x4a 0x09>;
interrupts = <0x00 0x109 0x08>;
clock-names = "TSF_CAMSYS_TSF_CGPDN";
};
scp_i2c2@105c7000 {
reg = <0x00 0x105c7000 0x00 0x1000>;
compatible = "mediatek,scp_i2c2";
};
mp1_cpucfg@0c530200 {
reg = <0x00 0xc530200 0x00 0x1000>;
compatible = "mediatek,mp1_cpucfg";
};
venc@17020000 {
phandle = <0x3b>;
reg = <0x00 0x17020000 0x00 0x1000>;
compatible = "mediatek,venc";
interrupts = <0x00 0xf7 0x08>;
};
imgsys1_vad@1502e000 {
reg = <0x00 0x1502e000 0x00 0x1000>;
compatible = "mediatek,imgsys1_vad";
};
otg_iddig {
phandle = <0xc2>;
usb_select_gpio = <0x1b 0x4e 0x00>;
status = "okay";
pinctrl-1 = <0x114>;
compatible = "mediatek,usb_iddig_bi_eint";
pinctrl-3 = <0x116>;
interrupt-parent = <0x1b>;
power_enable_gpio = <0x1b 0x35 0x00>;
interrupts = <0x18 0x08 0x18 0x00>;
usb_dk_detect_gpio = <0x1b 0x18 0x00>;
pinctrl-0 = <0x113>;
pinctrl-2 = <0x115>;
pinctrl-names = "iddig_default\0id_init\0id_enable\0id_disable";
};
mt_soc_fm_mrgtx_pcm {
compatible = "mediatek,mt_soc_pcm_fmtx";
};
simif1@80040000 {
reg = <0x00 0x80040000 0x00 0x1000>;
compatible = "mediatek,simif1";
};
dvfsp@10227000 {
reg = <0x00 0x10227000 0x00 0x1000>;
compatible = "mediatek,dvfsp";
interrupts = <0x00 0xab 0x08>;
};
sleep@10006000 {
reg = <0x00 0x10006000 0x00 0x1000>;
compatible = "mediatek,sleep";
interrupts = <0x00 0xbb 0x08>;
wakeup-source = <0x28 0x00 0x04 0x29 0x01 0x20 0x2a 0x03 0x2000000>;
};
camsv3@1a052000 {
reg = <0x00 0x1a052000 0x00 0x1000>;
compatible = "mediatek,camsv3";
interrupts = <0x00 0x104 0x08>;
};
serial@11004000 {
dmas = <0x41 0x04 0x41 0x05>;
phandle = <0x97>;
reg = <0x00 0x11004000 0x00 0x1000>;
compatible = "mediatek,mt6577-uart";
dma-names = "tx\0rx";
clocks = <0x2c 0x15 0x17>;
interrupts = <0x00 0x5d 0x08>;
clock-names = "baud\0bus";
};
mt_soc_voice_md1_bt {
compatible = "mediatek,mt_soc_pcm_voice_md1_bt";
};
mdsys_mbist_config@80360000 {
reg = <0x00 0x80360000 0x00 0x1000>;
compatible = "mediatek,mdsys_mbist_config";
};
iocfg_5@11d20000 {
phandle = <0x24>;
reg = <0x00 0x11d20000 0x00 0x1000>;
compatible = "mediatek,iocfg_5\0syscon";
};
disp_gamma0@14011000 {
reg = <0x00 0x14011000 0x00 0x1000>;
compatible = "mediatek,disp_gamma0";
interrupts = <0x00 0xea 0x08>;
};
smi_larb4@17010000 {
reg = <0x00 0x17010000 0x00 0x1000>;
compatible = "mediatek,smi_larb4\0mediatek,smi_larb";
mediatek,smi-id = <0x04>;
clocks = <0x2e 0x06 0x48 0x01 0x48 0x02 0x48 0x03>;
interrupts = <0x00 0xf8 0x08>;
clock-names = "mtcmos-ven\0venc-larb4\0venc-venc\0venc-jpgenc";
};
uea_uia_u1@87610000 {
reg = <0x00 0x87610000 0x00 0x1000>;
compatible = "mediatek,uea_uia_u1";
};
vpu_core1@0x19200000 {
reg = <0x00 0x19200000 0x00 0x94000>;
compatible = "mediatek,vpu_core1";
interrupts = <0x00 0x125 0x08>;
};
mt_soc_pcm_voice_ultra {
compatible = "mediatek,mt_soc_pcm_voice_ultra";
};
mt_soc_ul1_pcm {
compatible = "mediatek,mt_soc_pcm_capture";
};
modem_lite_topsm@83010000 {
reg = <0x00 0x83010000 0x00 0x1000>;
compatible = "mediatek,modem_lite_topsm";
};
idc_suart@80207000 {
reg = <0x00 0x80207000 0x00 0x1000>;
compatible = "mediatek,idc_suart";
};
mipi_rx_ana_csi2a@11c84000 {
reg = <0x00 0x11c84000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi2a";
};
md_clksw@80150000 {
reg = <0x00 0x80150000 0x00 0x1000>;
compatible = "mediatek,md_clksw";
};
mdm_psys_mbistcon@8020e000 {
reg = <0x00 0x8020e000 0x00 0x1000>;
compatible = "mediatek,mdm_psys_mbistcon";
};
seninf8@1a047000 {
reg = <0x00 0x1a047000 0x00 0x1000>;
compatible = "mediatek,seninf8";
};
searcher@87850000 {
reg = <0x00 0x87850000 0x00 0x1000>;
compatible = "mediatek,searcher";
};
pfc_encode@870c0000 {
reg = <0x00 0x870c0000 0x00 0x1000>;
compatible = "mediatek,pfc_encode";
};
mt_soc_pcm_voice_usb_echoref {
compatible = "mediatek,mt_soc_pcm_voice_usb_echoref";
};
dramc@1022a000 {
reg = <0x00 0x1022a000 0x00 0x2000 0x00 0x10232000 0x00 0x2000 0x00 0x1022c000 0x00 0x1000 0x00 0x10234000 0x00 0x1000 0x00 0x10228000 0x00 0x2000 0x00 0x10230000 0x00 0x2000 0x00 0x1022e000 0x00 0x1000 0x00 0x10236000 0x00 0x1000>;
compatible = "mediatek,dramc";
};
tdma@83020000 {
reg = <0x00 0x83020000 0x00 0x1000>;
compatible = "mediatek,tdma";
};
md_uart1@80330000 {
reg = <0x00 0x80330000 0x00 0x1000>;
compatible = "mediatek,md_uart1";
};
disp_rdma0@1400b000 {
reg = <0x00 0x1400b000 0x00 0x1000>;
compatible = "mediatek,disp_rdma0";
interrupts = <0x00 0xe4 0x08>;
};
l2sooutdma@85070000 {
reg = <0x00 0x85070000 0x00 0x1000>;
compatible = "mediatek,l2sooutdma";
};
pfc_decode@870d0000 {
reg = <0x00 0x870d0000 0x00 0x1000>;
compatible = "mediatek,pfc_decode";
};
l2dlbuf@850f0000 {
reg = <0x00 0x850f0000 0x00 0x1000>;
compatible = "mediatek,l2dlbuf";
};
imgsys@15020000 {
phandle = <0x49>;
reg = <0x00 0x15020000 0x00 0x1000>;
compatible = "mediatek,imgsys\0syscon";
#clock-cells = <0x01>;
clocks = <0x49 0x0a 0x49 0x08>;
clock-names = "DIP_CG_IMG_LARB5\0DIP_CG_IMG_DIP";
};
dbi@1401d000 {
reg = <0x00 0x1401d000 0x00 0x1000>;
compatible = "mediatek,dbi";
interrupts = <0x00 0xf4 0x08>;
};
l2mbist@85040000 {
reg = <0x00 0x85040000 0x00 0x1000>;
compatible = "mediatek,l2mbist";
};
spi1@11010000 {
mediatek,pad-select = <0x00>;
phandle = <0x99>;
reg = <0x00 0x11010000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x39>;
interrupts = <0x00 0x7c 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
gcu@83060000 {
reg = <0x00 0x83060000 0x00 0x1000>;
compatible = "mediatek,gcu";
};
iocfg_4@11d30000 {
phandle = <0x23>;
reg = <0x00 0x11d30000 0x00 0x1000>;
compatible = "mediatek,iocfg_4\0syscon";
};
imgsyscq@15020000 {
reg = <0x00 0x15020000 0x00 0x10>;
compatible = "mediatek,imgsyscq";
};
l2hwlog@85058000 {
reg = <0x00 0x85058000 0x00 0x1000>;
compatible = "mediatek,l2hwlog";
};
i2c@1101b000 {
phandle = <0x5e>;
mediatek,use-open-drain;
reg = <0x00 0x1101b000 0x00 0x1000 0x00 0x11000700 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x64 0x15 0x2b>;
interrupts = <0x00 0x59 0x08>;
id = <0x08>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
};
md_debug1@80080000 {
reg = <0x00 0x80080000 0x00 0x1000>;
compatible = "mediatek,md_debug1";
};
md_ost@f00e0000 {
reg = <0x00 0xf00e0000 0x00 0x1000>;
compatible = "mediatek,md_ost";
};
mt_soc_pcm_dl1_scp_spk {
compatible = "mediatek,mt_soc_pcm_dl1_scp_spk";
};
bpi_3g@87080000 {
reg = <0x00 0x87080000 0x00 0x1000>;
compatible = "mediatek,bpi_3g";
};
md_ccif1@1020c000 {
reg = <0x00 0x1020c000 0x00 0x1000>;
compatible = "mediatek,md_ccif1";
};
infra_mbist@1020d000 {
reg = <0x00 0x1020d000 0x00 0x1000>;
compatible = "mediatek,infra_mbist";
};
mdp_aal@1401b000 {
phandle = <0x38>;
reg = <0x00 0x1401b000 0x00 0x1000>;
compatible = "mediatek,mdp_aal";
clocks = <0x2f 0x2b>;
interrupts = <0x00 0xf2 0x08>;
clock-names = "MDP_AAL";
};
gcpu_rsa@1021a000 {
reg = <0x00 0x1021a000 0x00 0x1000>;
compatible = "mediatek,gcpu_rsa";
};
smi_larb1@16010000 {
reg = <0x00 0x16010000 0x00 0x1000>;
compatible = "mediatek,smi_larb1\0mediatek,smi_larb";
mediatek,smi-id = <0x01>;
clocks = <0x2e 0x0d 0x47 0x02 0x47 0x01>;
interrupts = <0x00 0x127 0x08>;
clock-names = "mtcmos-vde\0vdec-larb1\0vdec-vdec";
};
md_topsm@f00d0000 {
reg = <0x00 0xf00d0000 0x00 0x1000>;
compatible = "mediatek,md_topsm";
};
pd_adapter {
phandle = <0xb6>;
compatible = "mediatek,pd_adapter";
adapter_name = "pd_adapter";
};
mt_soc_routing_dai_name {
compatible = "mediatek,mt_soc_dai_routing";
};
irdma@82cb0000 {
reg = <0x00 0x82cb0000 0x00 0x1000>;
compatible = "mediatek,irdma";
};
spi0@1100a000 {
mediatek,pad-select = <0x00>;
phandle = <0x98>;
reg = <0x00 0x1100a000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x1c>;
interrupts = <0x00 0x78 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
psmcu_busmon@80210000 {
reg = <0x00 0x80210000 0x00 0x1000>;
compatible = "mediatek,psmcu_busmon";
};
pwrap_md32@10448000 {
reg = <0x00 0x10448000 0x00 0x1000>;
compatible = "mediatek,pwrap_md32";
};
wpe_a@1502a000 {
reg = <0x00 0x1502a000 0x00 0x1000>;
compatible = "mediatek,wpe_a";
clocks = <0x49 0x03>;
interrupts = <0x00 0x111 0x08>;
clock-names = "WPE_CLK_IMG_WPE_A";
};
mcucfg_mp2_counter@0c532000 {
reg = <0x00 0xc532000 0x00 0x1000>;
compatible = "mediatek,mcucfg_mp2_counter";
};
log3g@878a0000 {
reg = <0x00 0x878a0000 0x00 0x1000>;
compatible = "mediatek,log3g";
};
md_config@80000000 {
reg = <0x00 0x80000000 0x00 0x1000>;
compatible = "mediatek,md_config";
};
smi_larb2@1502f000 {
reg = <0x00 0x1502f000 0x00 0x1000>;
compatible = "mediatek,smi_larb2\0mediatek,smi_larb";
mediatek,smi-id = <0x02>;
clocks = <0x2e 0x05 0x2f 0x0a 0x49 0x09>;
interrupts = <0x00 0x107 0x08>;
clock-names = "mtcmos-isp\0gals-ipu2mm\0img-larb2";
};
md_i2c@80100000 {
reg = <0x00 0x80100000 0x00 0x1000>;
compatible = "mediatek,md_i2c";
};
mt6370_pmu_eint {
phandle = <0xb8>;
status = "okay";
interrupt-parent = <0x1b>;
interrupts = <0x0a 0x08 0x0a 0x00>;
};
l2ulhbdma@85010000 {
reg = <0x00 0x85010000 0x00 0x1000>;
compatible = "mediatek,l2ulhbdma";
};
disp_ovl0_2l@14009000 {
reg = <0x00 0x14009000 0x00 0x1000>;
compatible = "mediatek,disp_ovl0_2l";
interrupts = <0x00 0xe2 0x08>;
};
mrdump_ext_rst {
phandle = <0x91>;
status = "okay";
compatible = "mediatek, mrdump_ext_rst-eint";
force_mode = "EINT";
mode = "IRQ";
};
apcldmain_ao@10014000 {
reg = <0x00 0x10014000 0x00 0x1000>;
compatible = "mediatek,apcldmain_ao";
};
scp_i2c1@105c6000 {
reg = <0x00 0x105c6000 0x00 0x1000>;
compatible = "mediatek,scp_i2c1";
};
mbist_ao@10013000 {
reg = <0x00 0x10013000 0x00 0x1000>;
compatible = "mediatek,mbist_ao";
};
mdp_rsz1@14004000 {
phandle = <0x34>;
reg = <0x00 0x14004000 0x00 0x1000>;
compatible = "mediatek,mdp_rsz1";
clocks = <0x2f 0x10>;
interrupts = <0x00 0xdd 0x08>;
clock-names = "MDP_RSZ1";
};
mt_soc_deep_buffer_dl_pcm {
compatible = "mediatek,mt_soc_pcm_deep_buffer_dl";
};
camsys@1a000000 {
phandle = <0x4a>;
reg = <0x00 0x1a000000 0x00 0x1000>;
compatible = "mediatek,camsys\0syscon";
#clock-cells = <0x01>;
clocks = <0x2e 0x03 0x2e 0x05 0x2e 0x09 0x4a 0x03 0x4a 0x04 0x4a 0x06 0x4a 0x07 0x4a 0x08>;
clock-names = "ISP_SCP_SYS_DIS\0ISP_SCP_SYS_ISP\0ISP_SCP_SYS_CAM\0CAMSYS_CAM_CGPDN\0CAMSYS_CAMTG_CGPDN\0CAMSYS_CAMSV0_CGPDN\0CAMSYS_CAMSV1_CGPDN\0CAMSYS_CAMSV2_CGPDN";
};
md_clkctl@80120000 {
reg = <0x00 0x80120000 0x00 0x1000>;
compatible = "mediatek,md_clkctl";
};
mcdi@0011b000 {
reg = <0x00 0x11b000 0x00 0x800>;
compatible = "mediatek,mt6771-mcdi";
};
txbrp@87680000 {
reg = <0x00 0x87680000 0x00 0x1000>;
compatible = "mediatek,txbrp";
};
security_ao@1001a000 {
reg = <0x00 0x1001a000 0x00 0x1000>;
compatible = "mediatek,security_ao";
};
l2pseuphy@85050000 {
reg = <0x00 0x85050000 0x00 0x1000>;
compatible = "mediatek,l2pseuphy";
};
camsv2@1a051000 {
reg = <0x00 0x1a051000 0x00 0x1000>;
compatible = "mediatek,camsv2";
interrupts = <0x00 0x103 0x08>;
};
md_global_con_dcm@80130000 {
reg = <0x00 0x80130000 0x00 0x1000>;
compatible = "mediatek,md_global_con_dcm";
};
scp_spi0@105cf000 {
reg = <0x00 0x105cf000 0x00 0x1000>;
compatible = "mediatek,scp_spi0";
};
gce_mbox@10238000 {
phandle = <0x40>;
reg = <0x00 0x10238000 0x00 0x1000>;
compatible = "mediatek,mailbox-gce";
#mbox-cells = <0x03>;
clocks = <0x15 0x09 0x15 0x19>;
interrupts = <0x00 0xa2 0x08 0x00 0xa3 0x08>;
clock-names = "gce\0gce-timer";
#gce-subsys-cells = <0x02>;
#gce-event-cells = <0x01>;
};
topmisc@10011000 {
reg = <0x00 0x10011000 0x00 0x1000>;
compatible = "mediatek,topmisc";
};
idma@82000000 {
reg = <0x00 0x82000000 0x00 0x1000>;
compatible = "mediatek,idma";
};
seninf7@1a046000 {
reg = <0x00 0x1a046000 0x00 0x1000>;
compatible = "mediatek,seninf7";
};
hspasys_2_confg@87400000 {
reg = <0x00 0x87400000 0x00 0x1000>;
compatible = "mediatek,hspasys_2_confg";
};
mali@13040000 {
reg = <0x00 0x13040000 0x00 0x4000>;
interrupt-names = "GPU\0MMU\0JOB";
compatible = "mediatek,mali\0arm,mali-midgard\0arm,mali-bifrost";
interrupts = <0x00 0x116 0x08 0x00 0x117 0x08 0x00 0x118 0x08>;
};
timer {
phandle = <0x52>;
compatible = "arm,armv8-timer";
clock-frequency = <0xc65d40>;
interrupt-parent = <0x11>;
interrupts = <0x01 0x0d 0x08 0x01 0x0e 0x08 0x01 0x0b 0x08 0x01 0x0a 0x08>;
};
l2dllmac@85090000 {
reg = <0x00 0x85090000 0x00 0x1000>;
compatible = "mediatek,l2dllmac";
};
md_debug3@800a0000 {
reg = <0x00 0x800a0000 0x00 0x1000>;
compatible = "mediatek,md_debug3";
};
msdc1_ins {
phandle = <0xbe>;
status = "okay";
interrupt-parent = <0x1b>;
interrupts = <0x03 0x04 0x03 0x00>;
deb-gpios = <0x1b 0x03 0x00>;
debounce = <0x3e800>;
};
l2sec@850b0000 {
reg = <0x00 0x850b0000 0x00 0x1000>;
compatible = "mediatek,l2sec";
};
odm {
phandle = <0xaf>;
compatible = "simple-bus";
led@6 {
data = <0x01>;
phandle = <0x120>;
led_mode = <0x05>;
compatible = "mediatek,lcd-backlight";
pwm_config = <0x04 0x00 0x00 0x00 0x00>;
};
panel@0 {
phandle = <0x121>;
status = "okay";
compatible = "es,es6311_anx6585_zigzag_wxga";
gpio_lcd_pwr_en = <0x1b 0x37 0x00>;
lcd_rst_pin = <0x1b 0x2d 0x00>;
};
elink_hallswitch {
phandle = <0x12a>;
compatible = "mediatek,hallswitch";
};
led@4 {
data = <0x01>;
phandle = <0x11e>;
led_mode = <0x00>;
compatible = "mediatek,keyboard-backlight";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
elink_lcm {
te = <0x2c>;
lcm_dvdd_gpio = <0x1b 0x37 0x00>;
phandle = <0x125>;
lcm_reset_gpio = <0x1b 0x2d 0x00>;
compatible = "mediatek,elink_lcm";
avdd = <0x38>;
dvdd = <0x37>;
lcm_bl_en = <0x1b 0x9e 0x00>;
lcm_avdd_gpio = <0x1b 0x38 0x00>;
bl_en = <0x9e>;
rst = <0x2d>;
lcm_te_gpio = <0x1b 0x2c 0x00>;
};
led@2 {
data = <0x01>;
phandle = <0x11c>;
led_mode = <0x00>;
compatible = "mediatek,blue";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
elink_usbkeyboard {
phandle = <0x127>;
compatible = "mediatek,usbkeyboard";
};
usb_c_pinctrl {
pinctrl-6 = <0x102>;
pinctrl-8 = <0x104>;
phandle = <0x123>;
status = "okay";
pinctrl-1 = <0xfd>;
pinctrl-11 = <0x107>;
compatible = "mediatek,usb_c_pinctrl";
pinctrl-3 = <0xff>;
pinctrl-5 = <0x101>;
pinctrl-7 = <0x103>;
pinctrl-9 = <0x105>;
pinctrl-0 = <0xfc>;
pinctrl-10 = <0x106>;
pinctrl-2 = <0xfe>;
pinctrl-12 = <0x108>;
pinctrl-names = "usb_default\0redrv_c1_init\0redrv_c1_low\0redrv_c1_hiz\0redrv_c1_high\0redrv_c2_init\0redrv_c2_low\0redrv_c2_hiz\0redrv_c2_high\0switch_sel1\0switch_sel2\0switch_enable\0switch_disable";
pinctrl-4 = <0x100>;
usb_switch-data {
c1_pin_val = <0x02>;
c1_pin_num = <0x15>;
sel_pin_val = <0x01>;
sel_pin_num = <0x1c>;
c2_pin_val = <0x02>;
c2_pin_num = <0x16>;
en_pin_val = <0x00>;
en_pin_num = <0x1b>;
};
};
elink_gpiokey {
hallswitch_debounce = <0xfa00>;
phandle = <0x128>;
status = "okay";
pinctrl-1 = <0x112>;
compatible = "mediatek,gpiokey";
hallswitch_flag = <0x08>;
pinctrl-0 = <0x111>;
hallswitch_gpio = <0x1b 0x02 0x00>;
pinctrl-names = "gpiokey_default\0gpiokey_init";
};
led@0 {
data = <0x01>;
phandle = <0x11a>;
led_mode = <0x00>;
compatible = "mediatek,red";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
vibrator@0 {
phandle = <0x122>;
compatible = "mediatek,vibrator";
vib_timer = <0x19>;
vib_vol = <0x0b>;
vib_limit = <0x0b>;
};
ite166121_hdmi@0 {
vcn18-supply = <0x78>;
phandle = <0x124>;
mediatek,hdmi_bridgeic_port = <0x03>;
vcn33-supply = <0x88>;
status = "okay";
pinctrl-1 = <0x10a>;
compatible = "mediatek,mt8183-hdmitx";
vrf12-supply = <0x73>;
pinctrl-0 = <0x109>;
hdmi_power_gpios = <0x1b 0xb1 0x00>;
pinctrl-names = "hdmi_poweron\0hdmi_poweroff";
};
elink_misc {
phandle = <0x126>;
compatible = "mediatek,elink_misc";
};
elink_agingtest {
phandle = <0x129>;
status = "disabled";
compatible = "mediatek,agingtest";
};
led@5 {
data = <0x01>;
phandle = <0x11f>;
led_mode = <0x00>;
compatible = "mediatek,button-backlight";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
led@3 {
data = <0x01>;
phandle = <0x11d>;
led_mode = <0x00>;
compatible = "mediatek,jogball-backlight";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
led@1 {
data = <0x01>;
phandle = <0x11b>;
led_mode = <0x00>;
compatible = "mediatek,green";
pwm_config = <0x00 0x00 0x00 0x00 0x00>;
};
};
modem_temp_share@10018000 {
reg = <0x00 0x10018000 0x00 0x1000>;
compatible = "mediatek,modem_temp_share";
};
mdafe@82cd0000 {
reg = <0x00 0x82cd0000 0x00 0x1000>;
compatible = "mediatek,mdafe";
};
bpi_bsi_slv2@10225000 {
reg = <0x00 0x10225000 0x00 0x1000>;
compatible = "mediatek,bpi_bsi_slv2";
};
ap_ccif1@1020b000 {
reg = <0x00 0x1020b000 0x00 0x1000>;
compatible = "mediatek,ap_ccif1";
interrupts = <0x00 0x99 0x08>;
};
iocfg_6@11c50000 {
phandle = <0x25>;
reg = <0x00 0x11c50000 0x00 0x1000>;
compatible = "mediatek,iocfg_6\0syscon";
};
mse {
phandle = <0xc0>;
};
mt_soc_uldlloopback_pcm {
compatible = "mediatek,mt_soc_pcm_uldlloopback";
};
disp_mutex@14016000 {
phandle = <0x30>;
reg = <0x00 0x14016000 0x00 0x1000>;
compatible = "mediatek,disp_mutex";
interrupts = <0x00 0xd9 0x08>;
};
disp_ovl1_2l@1400a000 {
reg = <0x00 0x1400a000 0x00 0x1000>;
compatible = "mediatek,disp_ovl1_2l";
interrupts = <0x00 0xe3 0x08>;
};
scp_cirq_eint@105ca000 {
reg = <0x00 0x105ca000 0x00 0x1000>;
compatible = "mediatek,scp_cirq_eint";
};
disp_split@14013000 {
reg = <0x00 0x14013000 0x00 0x1000>;
compatible = "mediatek,disp_split";
};
mt_soc_anc_pcm {
compatible = "mediatek,mt_soc_pcm_anc";
};
mipi_rx_ana_csi1b@11c83000 {
reg = <0x00 0x11c83000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi1b";
};
a7_cirq@f0420000 {
reg = <0x00 0xf0420000 0x00 0x1000>;
compatible = "mediatek,a7_cirq";
};
i2c@11015000 {
phandle = <0x60>;
mediatek,use-open-drain;
reg = <0x00 0x11015000 0x00 0x1000 0x00 0x11000300 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x4b 0x15 0x2b 0x15 0x4a>;
interrupts = <0x00 0x84 0x08>;
id = <0x0a>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
clock-div = <0x05>;
};
efusec@11f10000 {
reg = <0x00 0x11f10000 0x00 0x1000>;
compatible = "mediatek,efusec";
};
l2sosecctl@850bc000 {
reg = <0x00 0x850bc000 0x00 0x1000>;
compatible = "mediatek,l2sosecctl";
};
mt_soc_hdmi_pcm {
compatible = "mediatek,mt_soc_pcm_hdmi";
};
apmixed@1000c000 {
phandle = <0x62>;
reg = <0x00 0x1000c000 0x00 0x1000>;
compatible = "mediatek,apmixed\0syscon";
#clock-cells = <0x01>;
};
divider@83040000 {
reg = <0x00 0x83040000 0x00 0x1000>;
compatible = "mediatek,divider";
};
owe_dma@1502c000 {
reg = <0x00 0x1502c000 0x00 0x1000>;
compatible = "mediatek,owe_dma";
};
rfic2_bsispi@80203000 {
reg = <0x00 0x80203000 0x00 0x1000>;
compatible = "mediatek,rfic2_bsispi";
};
gyro {
phandle = <0xbf>;
};
mfg_dfp_60@13020000 {
reg = <0x00 0x13020000 0x00 0x1000>;
compatible = "mediatek,mfg_dfp_60";
interrupts = <0x00 0x11a 0x08>;
};
bpi_bsi_slv1@1021f000 {
reg = <0x00 0x1021f000 0x00 0x1000>;
compatible = "mediatek,bpi_bsi_slv1";
};
csd_acc@82c70000 {
reg = <0x00 0x82c70000 0x00 0x1000>;
compatible = "mediatek,csd_acc";
};
scp_dvfs {
compatible = "mediatek,scp_dvfs";
clocks = <0x42 0x0f 0x2c 0x42 0x42 0x42 0x2e 0x42 0x30 0x42 0x40 0x42 0x2d 0x42 0x3d>;
clock-names = "clk_mux\0clk_pll_0\0clk_pll_1\0clk_pll_2\0clk_pll_3\0clk_pll_4\0clk_pll_5\0clk_pll_6";
};
l2soindma@85060000 {
reg = <0x00 0x85060000 0x00 0x1000>;
compatible = "mediatek,l2soindma";
};
apcldmain@1021b000 {
reg = <0x00 0x1021b000 0x00 0x1000>;
compatible = "mediatek,apcldmain";
};
usb3_xhci@11200000 {
phandle = <0xa0>;
reg = <0x00 0x11200000 0x00 0x1000>;
phys = <0x43 0x00>;
interrupt-names = "xhci";
compatible = "mediatek,mt67xx-xhci";
clocks = <0x15 0x3e>;
interrupts = <0x00 0x49 0x08>;
reg-names = "mac";
clock-names = "sys_ck";
phy-names = "port0_phy";
};
mcu_misccfg@0c530400 {
reg = <0x00 0xc530400 0x00 0x1000>;
compatible = "mediatek,mcu_misccfg";
};
ca9peri@10e00000 {
reg = <0x00 0x10e00000 0x00 0x1000>;
compatible = "mediatek,ca9peri";
};
auxadc@11001000 {
phandle = <0x95>;
reg = <0x00 0x11001000 0x00 0x1000>;
compatible = "mediatek,auxadc";
clocks = <0x15 0x24>;
interrupts = <0x00 0x4a 0x02>;
clock-names = "auxadc-main";
adc_channel@ {
mediatek,temperature1 = <0x01>;
status = "okay";
compatible = "mediatek,adc_channel";
mediatek,temperature0 = <0x00>;
mediatek,adc_fdd_rf_params_dynamic_custom_ch = <0x02>;
};
};
mt6370_pmu_dts {
interrupt-controller;
phandle = <0xca>;
mt6370,intr_gpio_num = <0x0a>;
mt6370,intr_gpio = <0x1b 0x0a 0x00>;
#interrupt-cells = <0x01>;
charger {
dc_wdt = "\0=\t";
enable_wdt;
load_switch_name = "primary_load_switch";
lbp_hys_sel = <0x01>;
lbp_dt = <0x01>;
interrupt-names = "chg_mivr\0chg_aiclmeasi\0attachi\0ovpctrl_uvp_d_evt\0chg_wdtmri\0chg_vbusov\0chg_tmri\0chg_treg\0dcdti";
ircmp_vclamp = <0x7d00>;
compatible = "mediatek,mt6370_pmu_charger";
fast_unknown_ta_dect;
charger_name = "primary_chg";
ircmp_resistor = <0x61a8>;
disable_vlgc;
aicr = <0x7a120>;
ieoc = <0x249f0>;
post_aicl;
enable_te;
mivr = <0x432380>;
safety_timer = <0x0c>;
ichg = <0x1e8480>;
cv = <0x426030>;
};
ldo {
interrupt-names = "ldo_oc";
ldo_oms = <0x01>;
compatible = "mediatek,mt6370_pmu_ldo";
ldo_vrc_lt = <0x01>;
mt6370_ldo {
regulator-name = "irtx_ldo";
regulator-min-microvolt = <0x186a00>;
regulator-max-microvolt = "\0=\t";
};
};
mt6370_pmu_fled1 {
fled_enable = <0x01>;
interrupt-names = "fled_lvf\0fled2_short\0fled1_short";
strobe_cur = <0x124f80>;
compatible = "mediatek,mt6370_pmu_fled1";
torch_cur = <0x493e0>;
strobe_timeout = <0x960>;
};
dsv {
db_single_pin = <0x00>;
db_vbst = <0x1644>;
db_startup = <0x00>;
db_vneg_20ms = <0x01>;
db_vneg_slew = <0x01>;
db_vneg_disc = <0x00>;
interrupt-names = "dsv_vneg_ocp\0dsv_vpos_ocp\0dsv_bst_ocp\0dsv_vneg_scp\0dsv_vpos_scp";
compatible = "mediatek,mt6370_pmu_dsv";
db_periodic_mode = <0x00>;
db_vpos_20ms = <0x01>;
db_vpos_slew = <0x01>;
db_periodic_fix = <0x00>;
db_delay = <0x03>;
db_vpos_disc = <0x01>;
db_freq_pm = <0x00>;
db_ext_en = <0x00>;
mt6370_dsvp {
regulator-name = "dsv_pos";
regulator-min-microvolt = "\0=\t";
regulator-max-microvolt = <0x5b8d80>;
};
mt6370_dsvn {
regulator-name = "dsv_neg";
regulator-min-microvolt = "\0=\t";
regulator-max-microvolt = <0x5b8d80>;
};
};
bled {
mt,pwm_avg_cycle = <0x00>;
mt,chan_en = <0x0f>;
mt,bled_ramptime = <0x03>;
mt,bled_name = "mt6370_pmu_bled";
mt,map_linear;
mt,pwm_fsample = <0x02>;
mt,bled_curr_scale = <0x00>;
interrupt-names = "bled_ocp";
mt,use_pwm;
compatible = "mediatek,mt6370_pmu_bled";
mt,bl_ovp_level = <0x03>;
mt,max_bled_brightness = <0x200>;
mt,pwm_hys = <0x00>;
mt,pwm_lpf_coef = <0x00>;
mt,pwm_deglitch = <0x01>;
mt,bled_flash_ramp = <0x01>;
mt,pwm_hys_en = <0x01>;
mt,bl_ocp_level = <0x02>;
};
rgbled {
interrupt-names = "isink4_short\0isink3_short\0isink2_short\0isink1_short\0isink4_open\0isink3_open\0isink2_open\0isink1_open";
compatible = "mediatek,mt6370_pmu_rgbled";
mt,led_default_trigger = "cc_mode\0cc_mode\0cc_mode\0none";
mt,led_name = "green\0red\0blue\0mt6370_pmu_led4";
};
core {
mrstb_tmr = <0x03>;
interrupt-names = "otp\0vdda_ovp\0vdda_uv";
int_wdt = <0x00>;
compatible = "mediatek,mt6370_pmu_core";
i2cstmr_rst_tmr = <0x00>;
mrstb_en;
int_deg = <0x00>;
};
mt6370_pmu_fled2 {
fled_enable = <0x01>;
strobe_cur = <0xf4240>;
compatible = "mediatek,mt6370_pmu_fled2";
torch_cur = <0x30d40>;
strobe_timeout = <0x4b0>;
};
};
disp_dither0@14012000 {
reg = <0x00 0x14012000 0x00 0x1000>;
compatible = "mediatek,disp_dither0";
interrupts = <0x00 0xeb 0x08>;
};
iocfg_3@11e90000 {
phandle = <0x22>;
reg = <0x00 0x11e90000 0x00 0x1000>;
compatible = "mediatek,iocfg_3\0syscon";
};
scp_i2c0@105c5000 {
reg = <0x00 0x105c5000 0x00 0x1000>;
compatible = "mediatek,scp_i2c0";
};
modem_lite_confg@83000000 {
reg = <0x00 0x83000000 0x00 0x1000>;
compatible = "mediatek,modem_lite_confg";
};
smi_common@14019000 {
reg = <0x00 0x14019000 0x00 0x1000>;
mmsys_config = <0x2f>;
compatible = "mediatek,smi_common";
mediatek,smi-id = <0x07>;
clocks = <0x2e 0x03 0x2f 0x04 0x2f 0x05 0x2f 0x01>;
clock-names = "mtcmos-mm\0smi-common-gals-comm0\0smi-common-gals-comm1\0smi-common";
};
mdp_rsz0@14003000 {
phandle = <0x33>;
reg = <0x00 0x14003000 0x00 0x1000>;
compatible = "mediatek,mdp_rsz0";
clocks = <0x2f 0x0f>;
interrupts = <0x00 0xdc 0x08>;
clock-names = "MDP_RSZ0";
};
fmem_smi@10238000 {
reg = <0x00 0x10238000 0x00 0x1000>;
compatible = "mediatek,fmem_smi";
};
mdl1ao@f60f0000 {
reg = <0x00 0xf60f0000 0x00 0x1000>;
compatible = "mediatek,mdl1ao";
};
firmware {
android {
compatible = "android,firmware";
serialno = "XXXXXXXXXXXXXXX";
mode = "normal";
hardware = "mt8788";
};
};
i2c@11007000 {
phandle = <0x56>;
mediatek,use-open-drain;
mediatek,skip_scp_sema;
reg = <0x00 0x11007000 0x00 0x1000 0x00 0x11000080 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x0b 0x15 0x2b>;
interrupts = <0x00 0x51 0x08>;
id = <0x00>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
goodix-hid-over-i2c@5d {
hid-descr-addr = <0x01>;
reg = <0x5d>;
status = "okay";
reg-tp-supply = <0x8a>;
compatible = "hid-over-i2c";
interrupt-parent = <0x1b>;
interrupts = <0x01 0x01 0x01 0x00>;
};
goodix_touch@5e {
reg = <0x5e>;
status = "okay";
reg-tp-supply = <0x8a>;
compatible = "mediatek,goodix_touch";
interrupt-parent = <0x1b>;
interrupts = <0x01 0x01 0x01 0x00>;
};
silead_touch@40 {
reg = <0x40>;
status = "okay";
reg-tp-supply = <0x8a>;
compatible = "mediatek,silead_touch";
interrupt-parent = <0x1b>;
interrupts = <0x01 0x01 0x01 0x00>;
};
cap_touch@38 {
rst-gpio = <0x1b 0x9e 0x00>;
reg = <0x38>;
status = "okay";
compatible = "mediatek,cap_touch";
int-gpio = <0x1b 0x01 0x00>;
interrupt-parent = <0x1b>;
interrupts = <0x01 0x01 0x01 0x00>;
};
};
cpu_dbgapb@0d410000 {
num = <0x08>;
phandle = <0x4f>;
reg = <0x00 0xd410000 0x00 0x1000 0x00 0xd510000 0x00 0x1000 0x00 0xd610000 0x00 0x1000 0x00 0xd710000 0x00 0x1000 0x00 0xd810000 0x00 0x1000 0x00 0xd910000 0x00 0x1000 0x00 0xda10000 0x00 0x1000 0x00 0xdb10000 0x00 0x1000>;
compatible = "mediatek,hw_dbg";
};
bsi_2g@83070000 {
reg = <0x00 0x83070000 0x00 0x1000>;
compatible = "mediatek,bsi_2g";
};
vdec_gcon@16000000 {
phandle = <0x47>;
reg = <0x00 0x16000000 0x00 0x1000>;
compatible = "mediatek,vdec_gcon\0syscon";
#clock-cells = <0x01>;
clocks = <0x2e 0x03 0x2e 0x0d 0x2e 0x06 0x47 0x01 0x48 0x02>;
clock-names = "MT_SCP_SYS_DIS\0MT_SCP_SYS_VDE\0MT_SCP_SYS_VEN\0MT_CG_VDEC\0MT_CG_VENC";
};
mt_soc_codec_name {
use_hp_depop_flow = <0x00>;
compatible = "mediatek,mt_soc_codec_63xx";
use_ul_260k = <0x00>;
pcbinfo = <0x1b 0xaf 0x00 0x1b 0x6f 0x00>;
};
md_peri_clk_ctl@800c0000 {
reg = <0x00 0x800c0000 0x00 0x1000>;
compatible = "mediatek,md_peri_clk_ctl";
};
camsv1@1a050000 {
reg = <0x00 0x1a050000 0x00 0x1000>;
compatible = "mediatek,camsv1";
interrupts = <0x00 0x102 0x08>;
};
dbg_tx@876d0000 {
reg = <0x00 0x876d0000 0x00 0x1000>;
compatible = "mediatek,dbg_tx";
};
gpufreq {
compatible = "mediatek,mt6771-gpufreq";
clocks = <0x42 0x04 0x42 0x61 0x2c 0x46 0x01 0x2e 0x07 0x2e 0x04 0x2e 0x0b 0x2e 0x0a 0x2e 0x0c>;
clock-names = "clk_mux\0clk_main_parent\0clk_sub_parent\0subsys_mfg_cg\0mtcmos_mfg_async\0mtcmos_mfg\0mtcmos_mfg_core0\0mtcmos_mfg_core1\0mtcmos_mfg_core2";
};
rt9465_slave_chr {
phandle = <0xb7>;
status = "okay";
compatible = "richtek,rt9465";
interrupt-parent = <0x1b>;
interrupts = <0x09 0x08 0x09 0x00>;
};
l2dlsbdma@85020000 {
reg = <0x00 0x85020000 0x00 0x1000>;
compatible = "mediatek,l2dlsbdma";
};
mt6370_pd_eint {
phandle = <0xba>;
status = "okay";
interrupt-parent = <0x1b>;
interrupts = <0x29 0x08 0x29 0x00>;
};
apc@82c30000 {
reg = <0x00 0x82c30000 0x00 0x1000>;
compatible = "mediatek,apc";
};
md_p_dma@80020000 {
reg = <0x00 0x80020000 0x00 0x1000>;
compatible = "mediatek,md_p_dma";
};
fingerprint {
phandle = <0xb9>;
compatible = "mediatek,goodix-fp";
};
md_ccif3@1023f000 {
reg = <0x00 0x1023f000 0x00 0x1000>;
compatible = "mediatek,md_ccif3";
};
seninf6@1a045000 {
reg = <0x00 0x1a045000 0x00 0x1000>;
compatible = "mediatek,seninf6";
};
ufshci@11270000 {
mediatek,spm-level = <0x03>;
vcc-supply = <0x14>;
phandle = <0xa3>;
reg = <0x00 0x11270000 0x00 0x2300>;
mediatek,spm_sw_mode;
mediatek,rpm-autosuspend-delay = <0x7d0>;
vcc-fixed-regulator;
compatible = "mediatek,ufshci";
mediatek,rpm-level = <0x03>;
clocks = <0x15 0x4f 0x15 0x3e 0x15 0x40 0x15 0x50>;
interrupts = <0x00 0x50 0x08>;
mediatek,auto-hibern8-timer = <0x0a>;
lanes-per-direction = <0x01>;
mediatek,rpm-enable = <0x01>;
clock-names = "ufs0-clock\0ufs0-unipro-clk\0ufs0-mp-clk\0ufs0-aes-clk";
freq-table-hz = <0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
};
dpa_bc@870b0000 {
reg = <0x00 0x870b0000 0x00 0x1000>;
compatible = "mediatek,dpa_bc";
};
mt_soc_dl1_awb_pcm {
compatible = "mediatek,mt_soc_pcm_dl1_awb";
};
mt_soc_ul2_pcm {
compatible = "mediatek,mt_soc_pcm_capture2";
};
fdvt@1502b000 {
reg = <0x00 0x1502b000 0x00 0x1000>;
compatible = "mediatek,fdvt";
clocks = <0x49 0x07>;
interrupts = <0x00 0x10d 0x08>;
clock-names = "FD_CLK_IMG_FDVT";
};
sleep_reg_md@1000f000 {
reg = <0x00 0x1000f000 0x00 0x1000>;
compatible = "mediatek,sleep_reg_md";
};
cam2@1a004000 {
reg = <0x00 0x1a004000 0x00 0x2000>;
compatible = "mediatek,cam2";
interrupts = <0x00 0xfe 0x08>;
};
wpe_b@1502d000 {
reg = <0x00 0x1502d000 0x00 0x1000>;
compatible = "mediatek,wpe_b";
clocks = <0x49 0x02>;
interrupts = <0x00 0x112 0x08>;
clock-names = "WPE_CLK_IMG_WPE_B";
};
topckgen_ao@1001b000 {
reg = <0x00 0x1001b000 0x00 0x1000>;
compatible = "mediatek,topckgen_ao";
};
afc_3g@87090000 {
reg = <0x00 0x87090000 0x00 0x1000>;
compatible = "mediatek,afc_3g";
};
accdet {
accdet-plugout-debounce = <0x01>;
accdet-mic-mode = <0x01>;
phandle = <0xa5>;
status = "okay";
compatible = "mediatek,pmic-accdet";
headset-eint-level-pol = <0x08>;
headset-three-key-threshold = <0x00 0x50 0xdc 0x190>;
headset-three-key-threshold-CDD = <0x00 0x79 0xc0 0x258>;
accdet-mic-vol = <0x06>;
interrupt-parent = <0x1b>;
interrupts = <0x07 0x08 0x07 0x00>;
headset-mode-setting = <0x500 0x500 0x01 0x1f0 0x800 0x800 0x20 0x44>;
deb-gpios = <0x1b 0x07 0x00>;
headset-four-key-threshold = <0x00 0x3a 0x79 0xc0 0x190>;
debounce = <0x3e800>;
};
usb3@11200000 {
dr_mode = "otg";
phandle = <0x9f>;
reg = <0x00 0x11201000 0x00 0x3000 0x00 0x11203e00 0x00 0x100>;
phys = <0x43 0x00>;
interrupt-names = "ssusb_mac";
compatible = "mediatek,mt6771-mtu3";
extcon = <0x44>;
clocks = <0x15 0x5b 0x15 0x3e>;
interrupts = <0x00 0x48 0x08>;
reg-names = "mac\0ippc";
clock-names = "sys_ck\0rel_clk";
phy-names = "port0_phy";
phy-cells = <0x01>;
};
mc_vmmu@16028000 {
reg = <0x00 0x16028000 0x00 0x1000>;
compatible = "mediatek,mc_vmmu";
};
md_eint@80110000 {
reg = <0x00 0x80110000 0x00 0x1000>;
compatible = "mediatek,md_eint";
};
l2ulsecctl@850b4000 {
reg = <0x00 0x850b4000 0x00 0x1000>;
compatible = "mediatek,l2ulsecctl";
};
als {
phandle = <0xc1>;
};
mipi_rx_ana_csi1a@11c82000 {
reg = <0x00 0x11c82000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi1a";
};
bfe@82ce0000 {
reg = <0x00 0x82ce0000 0x00 0x1000>;
compatible = "mediatek,bfe";
};
dip6@15027000 {
reg = <0x00 0x15027000 0x00 0x1000>;
compatible = "mediatek,dip6";
};
dvfsp@0011bc00 {
reg = <0x00 0x11bc00 0x00 0x1400 0x00 0x11bc00 0x00 0x1400>;
compatible = "mediatek,mt6771-dvfsp";
};
mt_soc_tdmrx_pcm {
compatible = "mediatek,mt_soc_tdm_capture";
};
mcucfg@0c530000 {
reg = <0x00 0xc530000 0x00 0x1000>;
compatible = "mediatek,mcucfg";
interrupts = <0x00 0x00 0x08>;
};
chosen {
ram_console = <0xd01100 0x80000 0x1000000 0xc00e0000>;
atag,shutdown_time = [38 39 34];
atag,videolfb = <0xae7c 0x00 0x1000000 0xa4170000 0xf201 0x68783832 0x37395f73 0x6c313031 0x706d3332 0x64313732 0x305f7775 0x7867615f 0x62303600 0x9bdbbb11>;
atag,mdinfo = <0x3000000 0x6080041 0x00>;
atag,videolfb-vramSize = <0x17bb000>;
atag,videolfb-islcmfound = <0x01>;
atag,boot_voltage = <0x33373837>;
plat_dbg_info,size = <0x40 0x18 0x00>;
log_store = <0xdf1100 0x10000>;
atag,ptp = <0x6000000 0x8004154 0x00 0x00 0x00 0x00>;
phandle = <0x4e>;
linux,initrd-start = <0x55000000>;
atag,devinfo = <0xc8000000 0x400 0x00 0x00 0x80000 0x730000 0x1000000 0x42001100 0x34000027 0x88070000 0x88070000 0x400ab56 0x60000000 0x9bdbbb11 0xe2691d65 0xba78ba5a 0x54527679 0x00 0xca0000 0x88070000 0x88070000 0x88070000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x88070000 0x00 0x34000000 0x00 0x6b400300 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x88070000 0x00 0x00 0x00 0x00 0x88070000 0x88070000 0xeeeeeeee 0x70004100 0x5fffffa0 0xcf47cf47 0x5fffffa0 0x55caffa0 0x8f4be847 0xaf9effa0 0x762ffa0 0x954be84b 0xb71ffa0 0x00 0x00 0x00 0x00 0x6e75fe26 0x4000000 0x40d1ffa0 0x9547e847 0x422bffa0 0x00 0x00 0x00 0x00 0x00 0x00 0x88070000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x88070000 0x88070000 0x7350a502 0x54611ea3 0xebd6aa 0xb8f71c84 0x628c9c7b 0xc818a58c 0x90 0x12102800 0x14000000 0x00 0x00 0x00 0x00 0xe7f91900 0x00 0x34e7c073 0xc073 0x00 0x00 0x00 0x40000000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x00 0x00 0x00 0x00 0x00 0x00 0xf8b5ed00 0xf8e08068 0x00 0x00 0x00 0x00 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0x88070000 0xf395e69a 0x1e6a86bc 0xfe046caa 0xf00fa417 0x2da7862a 0xfd6bcba2 0xf6ba883b 0x13d5c42c>;
plat_dbg_info,max = <0x03>;
atag,fg_swocv_v = [33 36 38 33 36];
plat_dbg_info,base = <0x11d80c 0x11d84c 0x00>;
plat_dbg_info,key = <0xd8a3 0xe31c 0x00>;
atag,masp = <0x16000000 0x66080041 0x22000000 0x22000000 0x00 0x00 0xa939ed5f 0x597bcf88 0x9fe6c2ac 0x93cb5496 0x31413532 0x41333637 0x43423132 0x43343538 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
kaslr-seed = <0x00 0x00>;
atag,boot = <0x3000000 0x2080041 0x00 0x2000000>;
ccci,modem_info_v2 = <0x5e9d 0x00 0x80020000 0x00 0x3000000 0x8000000 0x00 0x00 0x00 0x00 0x00 0x00>;
atag,videolfb-fb_base_h = <0x00>;
atag,videolfb-lcmname = "es6311_anx6585_zigzag_wxga";
bootargs = "console=tty0 console=ttyS0,921600n1 vmalloc=400M slub_debug=OFZPU swiotlb=noforce page_owner=on cgroup.memory=nosocket,nokmem androidboot.hardware=mt6771 firmware_class.path=/vendor/firmware loop.max_part=7 has_battery_removed=0 androidboot.boot_devices=bootdevice,11230000.mmc root=/dev/ram androidboot.verifiedbootstate=orange bootopt=64S3,32N2,64N2 buildvariant=user ddr_name= ddr_speed=0 androidboot.atm=disabled androidboot.meta_log_disable=0 printk.disable_uart=1 bootprof.pl_t=1168 bootprof.lk_t=7271 bootprof.logo_t=1109 androidboot.serialno=XXXXXXXXXXXXXXX androidboot.bootreason=PowerKey gpt=1 usb2jtag_mode=0 mrdump_ddrsv=yes mrdump_cb=0x11e000,0x2000 androidboot.dtb_idx=0 androidboot.dtbo_idx=0";
atag,videolfb-islcm_inited = <0x00>;
atag,fg_swocv_i = [2d 39 36 38 30];
atag,videolfb-fb_base_l = "^`P";
linux,initrd-end = <0x551323c8>;
atag,mem = <0x6000000 0x2004254 0x00 0x00 0x00 0x00 0x6000000 0x2004254 0x00 0x00 0x00 0x00>;
non_secure_sram = <0xa01200 0x600000>;
atag,imix_r = <0x7e000000>;
atag,two_sec_reboot = [30];
atag,videolfb-fps = <0x1770>;
};
rake_1@87830000 {
reg = <0x00 0x87830000 0x00 0x1000>;
compatible = "mediatek,rake_1";
};
mtk-btcvsd-snd@18000000 {
mediatek,infracfg = <0x15>;
phandle = <0x45>;
reg = <0x00 0x18000000 0x00 0x1000 0x00 0x18080000 0x00 0x10000>;
compatible = "mediatek,mtk-btcvsd-snd";
mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>;
interrupts = <0x00 0x120 0x08>;
};
mali_tb@1307f000 {
reg = <0x00 0x1307f000 0x00 0x1000>;
compatible = "mediatek,mali_tb";
};
bpi_bsi_slv0@1021e000 {
reg = <0x00 0x1021e000 0x00 0x1000>;
compatible = "mediatek,bpi_bsi_slv0";
};
audio_sram@11221000 {
reg = <0x00 0x11221000 0x00 0xc000>;
compatible = "mediatek,audio_sram";
};
mipi1_bsispi@80206000 {
reg = <0x00 0x80206000 0x00 0x1000>;
compatible = "mediatek,mipi1_bsispi";
};
mjc_config@12000000 {
reg = <0x00 0x12000000 0x00 0x1000>;
compatible = "mediatek,mjc_config";
};
scp_clk_ctrl@105c4000 {
reg = <0x00 0x105c4000 0x00 0x1000>;
compatible = "mediatek,scp_clk_ctrl";
};
mt_soc_voip_bt_out {
compatible = "mediatek,mt_soc_pcm_dl1_bt";
};
serial@11003000 {
dmas = <0x41 0x02 0x41 0x03>;
phandle = <0x96>;
reg = <0x00 0x11003000 0x00 0x1000>;
compatible = "mediatek,mt6577-uart";
dma-names = "tx\0rx";
clocks = <0x2c 0x15 0x16>;
interrupts = <0x00 0x5c 0x08>;
clock-names = "baud\0bus";
};
mt_soc_voice_md2 {
compatible = "mediatek,mt_soc_pcm_voice_md2";
};
extcon_usb {
phandle = <0x44>;
compatible = "mediatek,extcon-usb";
};
scp_timer@105c3000 {
reg = <0x00 0x105c3000 0x00 0x1000>;
compatible = "mediatek,scp_timer";
};
ahb2dspio@82800000 {
reg = <0x00 0x82800000 0x00 0x1000>;
compatible = "mediatek,ahb2dspio";
};
ap_ccif3@1023e000 {
reg = <0x00 0x1023e000 0x00 0x1000>;
compatible = "mediatek,ap_ccif3";
interrupts = <0x00 0x9d 0x08>;
};
md_elm@80250000 {
reg = <0x00 0x80250000 0x00 0x1000>;
compatible = "mediatek,md_elm";
};
scp_uart@105c9000 {
reg = <0x00 0x105c9000 0x00 0x1000>;
compatible = "mediatek,scp_uart";
};
cam4@1a008000 {
reg = <0x00 0x1a008000 0x00 0x2000>;
compatible = "mediatek,cam4";
interrupts = <0x00 0x100 0x08>;
};
type_c_port0 {
mt-tcpc,vconn_supply = <0x01>;
mt6370pd,intr_gpio_num = <0x29>;
phandle = <0xcb>;
mt-tcpc,role_def = <0x04>;
tcpc-dual,supported_modes = <0x00>;
mt-tcpc,rp_level = <0x00>;
mt-tcpc,name = "type_c_port0";
mt-tcpc,notifier_supply_num = <0x03>;
mt6370pd,intr_gpio = <0x1b 0x29 0x00>;
dpm_caps {
local_dr_data;
attemp_discover_cable;
dr_check = <0x00>;
local_no_suspend;
pr_check_gp_source;
local_dr_power;
attemp_enter_dp_mode;
local_usb_comm;
local_vconn_supply;
attemp_discover_id;
pr_check = <0x00>;
};
pd-data {
pd,country_nr = <0x00>;
pd,sink-pdo-data = <0x190c8 0xc0761e3c>;
pd,sink-pdo-size = <0x02>;
pd,source-pdo-data = <0x19032>;
bat,nr = <0x01>;
pd,id-vdo-data = <0xd10029cf 0x00 0x10000>;
pd,source-pdo-size = <0x01>;
pd,id-vdo-size = <0x03>;
pd,mfrs = "RichtekTCPC";
pd,vid = <0x29cf>;
pd,source-cap-ext = <0x171129cf 0x00 0x102 0x00 0x00 0x2000000>;
pd,pid = <0x5081>;
pd,charging_policy = <0x21>;
bat-info0 {
bat,mfrs = "bat1";
bat,vid = <0x29cf>;
bat,design_cap = <0xbb8>;
bat,pid = <0x1711>;
};
};
};
infracfg_ao@10001000 {
phandle = <0x15>;
reg = <0x00 0x10001000 0x00 0x1000>;
compatible = "mediatek,infracfg_ao\0syscon";
#clock-cells = <0x01>;
interrupts = <0x00 0x96 0x01>;
};
apcldmaout@1021b400 {
reg = <0x00 0x1021b400 0x00 0x1000>;
compatible = "mediatek,apcldmaout";
};
mjc_top@12001000 {
reg = <0x00 0x12001000 0x00 0x1000>;
compatible = "mediatek,mjc_top";
};
hspasys_3_confg@f0910000 {
reg = <0x00 0xf0910000 0x00 0x1000>;
compatible = "mediatek,hspasys_3_confg";
};
infra_md@1021d000 {
reg = <0x00 0x1021d000 0x00 0x1000>;
compatible = "mediatek,infra_md";
};
mdp_wdma@14006000 {
phandle = <0x36>;
reg = <0x00 0x14006000 0x00 0x1000>;
compatible = "mediatek,mdp_wdma";
clocks = <0x2f 0x2a>;
interrupts = <0x00 0xe0 0x08>;
clock-names = "MDP_WDMA";
};
smi_larb6@1a001000 {
reg = <0x00 0x1a001000 0x00 0x1000>;
compatible = "mediatek,smi_larb6\0mediatek,smi_larb";
mediatek,smi-id = <0x06>;
clocks = <0x2e 0x09 0x2f 0x09 0x4a 0x01>;
clock-names = "mtcmos-cam\0gals-cam2mm\0cam-larb6";
};
msdc@11230000 {
host_function = [00];
register_setting = <0x13>;
cap-mmc-highspeed;
pinctl_hs200 = <0x12>;
max-frequency = <0xbebc200>;
phandle = <0x3c>;
reg = <0x00 0x11230000 0x00 0x10000>;
pinctl = <0x12>;
status = "okay";
compatible = "mediatek,msdc";
mmc-ddr-1_8v;
hw_dvfs = [00];
index = [00];
vmmc-supply = <0x14>;
bootable;
clocks = <0x15 0x20 0x15 0x1d>;
interrupts = <0x00 0x4d 0x08>;
mmc-hs400-1_8v;
non-removable;
bus-width = <0x08>;
mmc-hs200-1_8v;
clock-names = "msdc0-clock\0msdc0-hclock";
pinctl_hs400 = <0x12>;
clk_src = [01];
msdc0@default {
phandle = <0x12>;
pins_cmd {
drive-strength = [04];
};
pins_rst {
drive-strength = [04];
};
pins_clk {
drive-strength = [04];
};
pins_ds {
drive-strength = [04];
};
pins_dat {
drive-strength = [04];
};
};
msdc0@register_default {
phandle = <0x13>;
wdata_edge = [00];
rdata_edge = [00];
cmd_edge = [00];
};
};
smi_larb3@1a002000 {
reg = <0x00 0x1a002000 0x00 0x1000>;
compatible = "mediatek,smi_larb3\0mediatek,smi_larb";
mediatek,smi-id = <0x03>;
clocks = <0x2e 0x09 0x2f 0x07 0x4a 0x0a>;
clock-names = "mtcmos-cam\0gals-ipu12mm\0cam-larb3";
};
mt_soc_mrgrx_pcm {
compatible = "mediatek,mt_soc_pcm_mrgrx";
};
mobicore {
compatible = "trustonic,mobicore";
interrupts = <0x00 0x130 0x01>;
};
md_attr_node {
mediatek,md_drdi_rf_set_idx = <0xf0f0f0f>;
compatible = "mediatek,md_attr_node";
mediatek,md_product_name_model_id = <0xf0f0f0f>;
};
avc_vld@16023000 {
reg = <0x00 0x16023000 0x00 0x1000>;
compatible = "mediatek,avc_vld";
};
vld2@16027800 {
reg = <0x00 0x16027800 0x00 0x1000>;
compatible = "mediatek,vld2";
};
seninf5@1a044000 {
reg = <0x00 0x1a044000 0x00 0x1000>;
compatible = "mediatek,seninf5";
};
iocfg_7@11f30000 {
phandle = <0x26>;
reg = <0x00 0x11f30000 0x00 0x1000>;
compatible = "mediatek,iocfg_7\0syscon";
};
venc_jpg@17030000 {
reg = <0x00 0x17030000 0x00 0x1000>;
compatible = "mediatek,venc_jpg";
clocks = <0x48 0x03>;
interrupts = <0x00 0xf9 0x08>;
clock-names = "MT_CG_VENC_JPGENC";
};
smart_pa {
phandle = <0xc5>;
};
i2c@1101a000 {
phandle = <0x5d>;
mediatek,use-open-drain;
reg = <0x00 0x1101a000 0x00 0x1000 0x00 0x11000680 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x63 0x15 0x2b>;
interrupts = <0x00 0x58 0x08>;
id = <0x07>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
};
tdd@84000000 {
reg = <0x00 0x84000000 0x00 0x1000>;
compatible = "mediatek,tdd";
};
cam1@1a003000 {
reg = <0x00 0x1a003000 0x00 0x1000>;
compatible = "mediatek,cam1";
interrupts = <0x00 0xfd 0x08>;
};
mp2_ca15m_config@0c532000 {
reg = <0x00 0xc532000 0x00 0x1000>;
compatible = "mediatek,mp2_ca15m_config";
};
mcu_misc1cfg@0c530800 {
reg = <0x00 0xc530800 0x00 0x1000>;
compatible = "mediatek,mcu_misc1cfg";
};
md1_sim2_hot_plug_eint {
phandle = <0xc7>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupt-parent = <0x11>;
interrupts = <0x01 0x07 0x08>;
};
vld_top@16021800 {
reg = <0x00 0x16021800 0x00 0x1000>;
compatible = "mediatek,vld_top";
};
cpus {
#size-cells = <0x00>;
#address-cells = <0x01>;
cpu@000 {
phandle = <0x09>;
enable-method = "psci";
reg = <0x00>;
compatible = "arm,cortex-a53";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu@103 {
phandle = <0x10>;
enable-method = "psci";
reg = <0x103>;
compatible = "arm,cortex-a73";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu@101 {
phandle = <0x0e>;
enable-method = "psci";
reg = <0x101>;
compatible = "arm,cortex-a73";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
idle-states {
entry-method = "arm,psci";
mcdi-cluster {
min-residency-us = <0x4b0>;
phandle = <0x04>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010001>;
exit-latency-us = <0x258>;
entry-latency-us = <0x258>;
};
dpidle {
min-residency-us = <0x7d0>;
phandle = <0x07>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010004>;
exit-latency-us = <0x3e8>;
entry-latency-us = <0x320>;
};
standby {
min-residency-us = <0x4b0>;
phandle = <0x02>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x01>;
exit-latency-us = <0x258>;
entry-latency-us = <0x258>;
};
suspend {
min-residency-us = <0x7d0>;
phandle = <0x08>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010005>;
exit-latency-us = <0x3e8>;
entry-latency-us = <0x320>;
};
sodi {
min-residency-us = <0x7d0>;
phandle = <0x05>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010002>;
exit-latency-us = <0x3e8>;
entry-latency-us = <0x320>;
};
sodi3 {
min-residency-us = <0x7d0>;
phandle = <0x06>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010003>;
exit-latency-us = <0x3e8>;
entry-latency-us = <0x320>;
};
mcdi-cpu {
min-residency-us = <0x4b0>;
phandle = <0x03>;
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x10001>;
exit-latency-us = <0x258>;
entry-latency-us = <0x258>;
};
};
cpu@003 {
phandle = <0x0c>;
enable-method = "psci";
reg = <0x03>;
compatible = "arm,cortex-a53";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu-map {
cluster0 {
core3 {
cpu = <0x0c>;
};
core1 {
cpu = <0x0a>;
};
core2 {
cpu = <0x0b>;
};
core0 {
cpu = <0x09>;
};
};
cluster1 {
core3 {
cpu = <0x10>;
};
core1 {
cpu = <0x0e>;
};
core2 {
cpu = <0x0f>;
};
core0 {
cpu = <0x0d>;
};
};
};
cpu@001 {
phandle = <0x0a>;
enable-method = "psci";
reg = <0x01>;
compatible = "arm,cortex-a53";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu@102 {
phandle = <0x0f>;
enable-method = "psci";
reg = <0x102>;
compatible = "arm,cortex-a73";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu@100 {
phandle = <0x0d>;
enable-method = "psci";
reg = <0x100>;
compatible = "arm,cortex-a73";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
cpu@002 {
phandle = <0x0b>;
enable-method = "psci";
reg = <0x02>;
compatible = "arm,cortex-a53";
device_type = "cpu";
cpu-idle-states = <0x02 0x03 0x04 0x05 0x06 0x07 0x08>;
clock-frequency = <0x8b799100>;
};
};
pwrap_p2p@1005e000 {
reg = <0x00 0x105cb000 0x00 0x1000>;
compatible = "mediatek,pwrap_p2p";
};
dip5@15026000 {
reg = <0x00 0x15026000 0x00 0x1000>;
compatible = "mediatek,dip5";
};
vp6@16027000 {
reg = <0x00 0x16027000 0x00 0x1000>;
compatible = "mediatek,vp6";
};
__symbols__ {
ssusb_ip_sleep = "/ssusb_ip_sleep";
mt_pmic_vusb_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vusb";
disp_color0 = "/disp_color0@1400e000";
mdp_rsz0 = "/mdp_rsz0@14003000";
goodix_fp = "/fingerprint";
radio_md_cfg = "/radio_md_cfg";
i2c10 = "/i2c@11015000";
mt_charger = "/mt_charger";
cpu0 = "/cpus/cpu@000";
infracfg_ao = "/infracfg_ao@10001000";
scp = "/scp@10500000";
mdcldma = "/mdcldma@10014000";
spi4 = "/spi4@11018000";
dsi_te = "/dsi_te";
mt_pmic_vcama2_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcama2";
mt_pmic_vxo22_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vxo22";
MCDI_CPU = "/cpus/idle-states/mcdi-cpu";
ipu0 = "/ipu0@19180000";
btcvsd_snd = "/mtk-btcvsd-snd@18000000";
i2c5 = "/i2c@11017000";
pmic_clock_buffer_ctrl = "/pmic_clock_buffer_ctrl";
msdc1 = "/msdc@11240000";
tcpc_pd = "/mt6370_pd_eint";
DPIDLE = "/cpus/idle-states/dpidle";
cpu2 = "/cpus/cpu@002";
md1_sim2_hot_plug_eint = "/md1_sim2_hot_plug_eint";
pio = "/1000b000.pinctrl";
iocfg_0 = "/iocfg_0@11f20000";
mt_pmic_vcn28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcn28";
auxadc = "/auxadc@11001000";
mt_pmic_vsram_gpu_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsram_gpu";
smart_pa = "/smart_pa";
apmixed = "/apmixed@1000c000";
venc_gcon = "/venc_gcon@17000000";
mt6358regulator = "/pwrap@1000d000/mt6358-pmic/mt6358regulator";
topckgen = "/topckgen@10000000";
mt_pmic_vmodem_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vmodem";
cpu_dbgapb = "/cpu_dbgapb@0d410000";
i2c7 = "/i2c@1101a000";
venc = "/venc@17020000";
mt_pmic_vsram_proc12_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsram_proc12";
extcon_usb = "/extcon_usb";
mt_pmic_vldo28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vldo28";
mt6358_rtc = "/pwrap@1000d000/mt6358-pmic/mt6358_rtc";
msdc1_pins_sdr104 = "/msdc@11240000/msdc1@sdr104";
mt_pmic_vcamio_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcamio";
cpu4 = "/cpus/cpu@100";
apuart0 = "/serial@11002000";
mt_pmic_vcn33_bt_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcn33_bt";
chosen = "/chosen";
mdp_wrot0 = "/mdp_wrot0@14005000";
iocfg_2 = "/iocfg_2@11e70000";
usb0 = "/usb3@11200000";
kd_camera_hw1 = "/kd_camera_hw1@1a040000";
als = "/als";
accdet = "/accdet";
eint = "/apirq@1000b000";
main_pmic = "/pwrap@1000d000/mt6358-pmic";
disp_mutex = "/disp_mutex@14016000";
mmsys_config = "/mmsys_config@14000000";
gpio_usage_mapping = "/gpio";
i2c9 = "/i2c@11014000";
rt9465_slave_chr = "/rt9465_slave_chr";
mtkfb = "/mtkfb@0";
audgpio = "/mt_soc_dl1_pcm@11220000";
mt_pmic_vio28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vio28";
mt_pmic_vdram2_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vdram2";
MCDI_CLUSTER = "/cpus/idle-states/mcdi-cluster";
cpu6 = "/cpus/cpu@102";
apuart2 = "/serial@11004000";
mt_pmic_vrf12_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vrf12";
mt_pmic_vcamd_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcamd";
iocfg_4 = "/iocfg_4@11d30000";
mdp_rdma1 = "/mdp_rdma1@14002000";
gyro = "/gyro";
ipu_adl = "/ipu_adl@19010000";
mhl = "/mhl@0";
i2c0 = "/i2c@11007000";
msdc1_pins_ddr50 = "/msdc@11240000/msdc1@ddr50";
mt_pmic_vcn18_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcn18";
reserved_memory = "/reserved-memory";
mse = "/mse";
spi1 = "/spi1@11010000";
odm = "/odm";
msdc1_ins = "/msdc1_ins";
pwraph = "/pwraphal@";
timer = "/timer";
clk_null = "/clocks/clk_null";
mt_pmic_vgpu_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vgpu";
iocfg_6 = "/iocfg_6@11c50000";
keypad = "/kp@10010000";
mrdump_ext_rst = "/mrdump_ext_rst";
pmic = "/pwrap@1000d000/mt6358-pmic/mt-pmic";
i2c2 = "/i2c@11009000";
pd_adapter = "/pd_adapter";
msdc1_pins_sdr50 = "/msdc@11240000/msdc1@sdr50";
mt_pmic_vaud28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vaud28";
spi3 = "/spi3@11013000";
SUSPEND = "/cpus/idle-states/suspend";
mt_pmic_va12_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_va12";
memory_ssmr_features = "/memory-ssmr-features";
usb_boost = "/usb_boost_manager";
mt6370_typec = "/type_c_port0";
mt_pmic_vsim1_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsim1";
mt_pmic_vio18_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vio18";
STANDBY = "/cpus/idle-states/standby";
usb0phy = "/usb0phy@11f40000";
mt_pmic_vfe28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vfe28";
consys = "/consys@18070000";
mt_pmic_vdram1_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vdram1";
xhci0 = "/usb3_xhci@11200000";
i2c4 = "/i2c@11008000";
mt_pmic_vs2_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vs2";
mdp_ccorr = "/mdp_ccorr@1401c000";
mt_pmic_vsram_others_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsram_others";
apdma = "/dma-controller@11000780";
otg_iddig = "/otg_iddig";
msdc0 = "/msdc@11230000";
mdp_rsz1 = "/mdp_rsz1@14004000";
flashlights_mt6370 = "/flashlights_mt6370";
i2c11 = "/i2c@11016000";
cpu1 = "/cpus/cpu@001";
md1_sim1_hot_plug_eint = "/md1_sim1_hot_plug_eint";
flashlight_core = "/flashlight_core";
spi5 = "/spi5@11019000";
smi_larb0 = "/smi_larb0@14017000";
mt_pmic_vibr_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vibr";
msdc0_register_setting_default = "/msdc@11230000/msdc0@register_default";
mt_pmic_vbif28_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vbif28";
imgsys = "/imgsys@15020000";
ipu1 = "/ipu1@19280000";
mt_pmic_vcama1_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcama1";
subpmic_pmu_eint = "/mt6370_pmu_eint";
gic = "/interrupt-controller@0c000000";
i2c_common = "/i2c_common";
i2c6 = "/i2c@11005000";
msdc1_register_setting_default = "/msdc@11240000/msdc1@register_default";
mt_pmic_vcn33_wifi_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vcn33_wifi";
nfc = "/nfc";
cpu3 = "/cpus/cpu@003";
mdp_wdma = "/mdp_wdma@14006000";
msdc1_pins_default = "/msdc@11240000/msdc1@default";
ufshci = "/ufshci@11270000";
mt6358_misc = "/pwrap@1000d000/mt6358-pmic/mt6358_misc";
disp_aal0 = "/disp_aal0@14010000";
gce_mbox = "/gce_mbox@10238000";
mt6370_pmu = "/mt6370_pmu_dts";
iocfg_1 = "/iocfg_1@11e80000";
mt_pmic_vproc12_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vproc12";
sysirq = "/intpol-controller@0c530620";
vdec_gcon = "/vdec_gcon@16000000";
mfgcfg = "/mfgcfg@13000000";
irtx_pwm = "/irtx_pwm";
i2c8 = "/i2c@1101b000";
clk26m = "/clocks/clk26m";
usb_c_pinctrl = "/usb_c_pinctrl";
mdp_aal = "/mdp_aal@1401b000";
mt_pmic_va09_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_va09";
mt_pmic_vsram_proc11_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsram_proc11";
mt_pmic_vs1_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vs1";
cpu5 = "/cpus/cpu@101";
irq_nfc = "/irq_nfc";
apuart1 = "/serial@11003000";
bat_gm30 = "/battery";
iocfg_3 = "/iocfg_3@11e90000";
ipu_conn = "/ipu_conn@19000000";
mdp_rdma0 = "/mdp_rdma0@14001000";
gpio = "/gpio@10005000";
wifi = "/wifi@180f0000";
mt_pmic_vefuse_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vefuse";
audio = "/audio@11220000";
camsys = "/camsys@1a000000";
mt_pmic_vemc_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vemc";
mt_pmic_vpa_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vpa";
clk32k = "/clocks/clk32k";
spi0 = "/spi0@1100a000";
cpu7 = "/cpus/cpu@103";
charger = "/charger";
lk_charger = "/lk_charger";
iocfg_5 = "/iocfg_5@11d20000";
hwrng = "/hwrng";
i2c1 = "/i2c@11011000";
SODI3 = "/cpus/idle-states/sodi3";
mt_pmic_vaux18_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vaux18";
mt_pmic_vproc11_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vproc11";
scpsys = "/scpsys@10001000";
SODI = "/cpus/idle-states/sodi";
pmic_auxadc = "/pwrap@1000d000/mt6358-pmic/mt635x-auxadc";
mt_pmic_vrf18_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vrf18";
spi2 = "/spi2@11012000";
touch = "/touch";
mt_pmic_vmc_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vmc";
rt5081_pmu_eint = "/rt5081_pmu_eint";
mt_pmic_vsim2_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vsim2";
mt_pmic_vcore_buck_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/buck_vcore";
dynamic_options = "/dynamic_options";
mdp_tdshp = "/mdp_tdshp@14007000";
mt_pmic_vmch_ldo_reg = "/pwrap@1000d000/mt6358-pmic/mt6358regulator/ldo_vmch";
iocfg_7 = "/iocfg_7@11f30000";
pwrap = "/pwrap@1000d000";
msdc0_pins_default = "/msdc@11230000/msdc0@default";
rt5081_pd = "/rt5081_pd_eint";
i2c3 = "/i2c@1100f000";
};
mdinfra_misc@803b0000 {
reg = <0x00 0x803b0000 0x00 0x1000>;
compatible = "mediatek,mdinfra_misc";
};
dpa_rlc@87620000 {
reg = <0x00 0x87620000 0x00 0x1000>;
compatible = "mediatek,dpa_rlc";
};
gpio@10005000 {
phandle = <0x1e>;
reg = <0x00 0x10005000 0x00 0x1000>;
compatible = "mediatek,gpio\0syscon";
gpio_init_default = <0x00 0x00 0x00 0x00 0x01 0x01 0x01 0x01 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x00 0x00 0x00 0x01 0x00 0x01 0x03 0x00 0x00 0x00 0x01 0x01 0x01 0x04 0x00 0x00 0x00 0x01 0x00 0x00 0x05 0x00 0x00 0x00 0x01 0x00 0x00 0x06 0x00 0x00 0x00 0x01 0x00 0x00 0x07 0x00 0x00 0x00 0x01 0x01 0x00 0x08 0x00 0x00 0x00 0x01 0x00 0x00 0x09 0x00 0x00 0x00 0x01 0x01 0x00 0x0a 0x00 0x00 0x00 0x01 0x01 0x00 0x0b 0x03 0x00 0x00 0x01 0x01 0x00 0x0c 0x03 0x00 0x00 0x01 0x01 0x00 0x0d 0x00 0x00 0x00 0x01 0x00 0x00 0x0e 0x00 0x00 0x00 0x01 0x00 0x00 0x0f 0x00 0x00 0x00 0x01 0x00 0x00 0x10 0x00 0x00 0x00 0x01 0x00 0x00 0x11 0x00 0x00 0x00 0x01 0x00 0x00 0x12 0x00 0x00 0x00 0x01 0x00 0x00 0x13 0x00 0x00 0x00 0x01 0x00 0x00 0x14 0x00 0x00 0x00 0x01 0x00 0x00 0x15 0x00 0x00 0x00 0x01 0x00 0x00 0x16 0x00 0x00 0x00 0x01 0x00 0x00 0x17 0x00 0x00 0x00 0x01 0x00 0x00 0x18 0x00 0x00 0x00 0x01 0x01 0x00 0x19 0x00 0x00 0x00 0x01 0x00 0x00 0x1a 0x00 0x00 0x00 0x01 0x00 0x00 0x1b 0x00 0x00 0x00 0x01 0x00 0x00 0x1c 0x00 0x00 0x00 0x01 0x00 0x00 0x1d 0x01 0x01 0x00 0x00 0x00 0x00 0x1e 0x01 0x00 0x00 0x01 0x01 0x00 0x1f 0x01 0x00 0x00 0x01 0x01 0x00 0x20 0x01 0x00 0x00 0x01 0x01 0x00 0x21 0x01 0x00 0x00 0x01 0x01 0x00 0x22 0x01 0x00 0x00 0x01 0x01 0x00 0x23 0x01 0x00 0x00 0x01 0x01 0x00 0x24 0x01 0x01 0x00 0x00 0x00 0x00 0x25 0x01 0x01 0x00 0x00 0x00 0x00 0x26 0x01 0x01 0x00 0x00 0x00 0x00 0x27 0x01 0x01 0x00 0x00 0x00 0x00 0x28 0x01 0x00 0x00 0x01 0x01 0x00 0x29 0x00 0x00 0x00 0x01 0x01 0x00 0x2a 0x00 0x01 0x00 0x00 0x00 0x00 0x2b 0x01 0x01 0x00 0x00 0x00 0x00 0x2c 0x00 0x00 0x00 0x01 0x00 0x00 0x2d 0x00 0x00 0x00 0x01 0x00 0x00 0x2e 0x00 0x00 0x00 0x01 0x00 0x00 0x2f 0x01 0x00 0x00 0x01 0x01 0x00 0x30 0x01 0x00 0x00 0x01 0x01 0x00 0x31 0x01 0x00 0x00 0x01 0x01 0x00 0x32 0x00 0x01 0x00 0x01 0x00 0x00 0x33 0x00 0x01 0x00 0x01 0x00 0x00 0x34 0x00 0x00 0x00 0x01 0x00 0x00 0x35 0x00 0x00 0x00 0x01 0x00 0x00 0x36 0x00 0x00 0x00 0x01 0x00 0x00 0x37 0x00 0x01 0x00 0x01 0x00 0x00 0x38 0x00 0x01 0x00 0x01 0x00 0x00 0x39 0x00 0x00 0x00 0x01 0x00 0x00 0x3a 0x00 0x00 0x00 0x01 0x00 0x00 0x3b 0x01 0x00 0x00 0x01 0x00 0x00 0x3c 0x01 0x00 0x00 0x01 0x00 0x00 0x3d 0x01 0x00 0x00 0x01 0x00 0x00 0x3e 0x01 0x00 0x00 0x01 0x00 0x00 0x3f 0x01 0x00 0x00 0x01 0x00 0x00 0x40 0x01 0x00 0x00 0x01 0x00 0x00 0x41 0x00 0x00 0x00 0x01 0x00 0x00 0x42 0x00 0x00 0x00 0x01 0x00 0x00 0x43 0x01 0x00 0x00 0x01 0x00 0x00 0x44 0x01 0x00 0x00 0x01 0x00 0x00 0x45 0x00 0x00 0x00 0x01 0x00 0x00 0x46 0x01 0x01 0x00 0x01 0x00 0x00 0x47 0x01 0x01 0x00 0x01 0x00 0x00 0x48 0x01 0x01 0x00 0x01 0x00 0x00 0x49 0x01 0x01 0x00 0x01 0x00 0x00 0x4a 0x01 0x00 0x00 0x01 0x00 0x00 0x4b 0x01 0x00 0x00 0x01 0x00 0x00 0x4c 0x01 0x01 0x00 0x01 0x00 0x00 0x4d 0x00 0x00 0x00 0x01 0x00 0x00 0x4e 0x00 0x00 0x00 0x01 0x00 0x00 0x4f 0x00 0x00 0x00 0x01 0x00 0x00 0x50 0x00 0x00 0x00 0x01 0x00 0x00 0x51 0x01 0x00 0x00 0x01 0x01 0x00 0x52 0x01 0x00 0x00 0x01 0x01 0x00 0x53 0x01 0x00 0x00 0x01 0x01 0x00 0x54 0x01 0x00 0x00 0x01 0x01 0x00 0x55 0x00 0x00 0x00 0x01 0x00 0x00 0x56 0x00 0x00 0x00 0x01 0x00 0x00 0x57 0x00 0x00 0x00 0x01 0x00 0x00 0x58 0x00 0x00 0x00 0x01 0x00 0x00 0x59 0x00 0x00 0x00 0x01 0x00 0x00 0x5a 0x00 0x00 0x00 0x01 0x00 0x00 0x5b 0x00 0x00 0x00 0x01 0x00 0x00 0x5c 0x01 0x01 0x00 0x01 0x00 0x00 0x5d 0x01 0x00 0x00 0x01 0x01 0x00 0x5e 0x00 0x00 0x00 0x01 0x00 0x00 0x5f 0x01 0x00 0x00 0x01 0x01 0x00 0x60 0x01 0x01 0x00 0x00 0x00 0x00 0x61 0x00 0x01 0x00 0x00 0x00 0x00 0x62 0x00 0x00 0x00 0x01 0x00 0x00 0x63 0x00 0x01 0x00 0x00 0x00 0x00 0x64 0x00 0x00 0x00 0x01 0x00 0x00 0x65 0x00 0x01 0x01 0x00 0x00 0x00 0x66 0x00 0x00 0x00 0x01 0x00 0x00 0x67 0x01 0x00 0x00 0x01 0x01 0x00 0x68 0x01 0x00 0x00 0x01 0x01 0x00 0x69 0x01 0x00 0x00 0x01 0x01 0x00 0x6a 0x01 0x00 0x00 0x01 0x01 0x00 0x6b 0x00 0x00 0x00 0x01 0x00 0x00 0x6c 0x00 0x00 0x00 0x01 0x00 0x00 0x6d 0x00 0x00 0x00 0x01 0x00 0x00 0x6e 0x00 0x00 0x00 0x01 0x00 0x00 0x6f 0x00 0x00 0x00 0x01 0x00 0x00 0x70 0x00 0x00 0x00 0x01 0x00 0x00 0x71 0x01 0x00 0x00 0x01 0x00 0x00 0x72 0x01 0x00 0x00 0x01 0x00 0x00 0x73 0x01 0x00 0x00 0x01 0x00 0x00 0x74 0x01 0x00 0x00 0x01 0x00 0x00 0x75 0x01 0x00 0x00 0x01 0x00 0x00 0x76 0x01 0x00 0x00 0x01 0x00 0x00 0x77 0x01 0x00 0x00 0x01 0x00 0x00 0x78 0x01 0x00 0x00 0x01 0x00 0x00 0x79 0x01 0x00 0x00 0x01 0x00 0x00 0x7a 0x01 0x00 0x00 0x01 0x01 0x00 0x7b 0x01 0x00 0x00 0x01 0x01 0x00 0x7c 0x01 0x01 0x00 0x00 0x00 0x00 0x7d 0x01 0x00 0x00 0x01 0x01 0x00 0x7e 0x01 0x00 0x00 0x01 0x01 0x00 0x7f 0x01 0x00 0x00 0x01 0x01 0x00 0x80 0x01 0x00 0x00 0x01 0x01 0x00 0x81 0x01 0x00 0x00 0x01 0x01 0x00 0x82 0x01 0x00 0x00 0x01 0x01 0x00 0x83 0x01 0x00 0x00 0x01 0x00 0x00 0x84 0x01 0x00 0x00 0x01 0x01 0x00 0x85 0x01 0x01 0x01 0x00 0x00 0x00 0x86 0x01 0x00 0x00 0x01 0x00 0x00 0x87 0x01 0x01 0x00 0x00 0x00 0x00 0x88 0x01 0x01 0x00 0x01 0x00 0x00 0x89 0x01 0x01 0x00 0x01 0x00 0x00 0x8a 0x01 0x01 0x00 0x00 0x00 0x00 0x8b 0x01 0x01 0x00 0x01 0x00 0x00 0x8c 0x01 0x00 0x00 0x00 0x00 0x00 0x8d 0x01 0x00 0x00 0x00 0x00 0x00 0x8e 0x01 0x00 0x00 0x00 0x00 0x00 0x8f 0x01 0x00 0x00 0x00 0x00 0x00 0x90 0x01 0x00 0x00 0x01 0x00 0x00 0x91 0x01 0x01 0x01 0x00 0x00 0x00 0x92 0x01 0x00 0x00 0x01 0x00 0x00 0x93 0x01 0x01 0x00 0x00 0x00 0x00 0x94 0x01 0x01 0x00 0x00 0x00 0x00 0x95 0x01 0x01 0x00 0x00 0x00 0x00 0x96 0x00 0x00 0x00 0x01 0x00 0x00 0x97 0x00 0x00 0x00 0x01 0x00 0x00 0x98 0x00 0x01 0x00 0x00 0x00 0x00 0x99 0x00 0x00 0x00 0x01 0x00 0x00 0x9a 0x01 0x01 0x00 0x00 0x00 0x00 0x9b 0x00 0x00 0x00 0x01 0x00 0x00 0x9c 0x00 0x00 0x00 0x01 0x00 0x00 0x9d 0x00 0x00 0x00 0x01 0x00 0x00 0x9e 0x00 0x01 0x00 0x00 0x00 0x00 0x9f 0x00 0x00 0x00 0x01 0x01 0x00 0xa0 0x00 0x00 0x00 0x01 0x01 0x00 0xa1 0x00 0x00 0x00 0x01 0x00 0x00 0xa2 0x00 0x00 0x00 0x01 0x00 0x00 0xa3 0x00 0x00 0x00 0x01 0x00 0x00 0xa4 0x00 0x00 0x00 0x01 0x00 0x00 0xa5 0x00 0x01 0x01 0x00 0x00 0x00 0xa6 0x00 0x00 0x00 0x01 0x00 0x00 0xa7 0x01 0x01 0x00 0x01 0x00 0x00 0xa8 0x01 0x01 0x00 0x01 0x00 0x00 0xa9 0x00 0x00 0x00 0x01 0x00 0x00 0xaa 0x00 0x00 0x00 0x01 0x00 0x00 0xab 0x00 0x00 0x00 0x01 0x00 0x00 0xac 0x00 0x00 0x00 0x01 0x00 0x00 0xad 0x00 0x00 0x00 0x01 0x00 0x00 0xae 0x00 0x00 0x00 0x01 0x00 0x00 0xaf 0x00 0x00 0x00 0x01 0x00 0x00 0xb0 0x00 0x00 0x00 0x01 0x00 0x00 0xb1 0x00 0x01 0x00 0x01 0x00 0x00 0xb2 0x00 0x00 0x00 0x01 0x00 0x00 0xb3 0x00 0x01 0x00 0x00 0x00 0x00 0xb4 0x00 0x00 0x00 0x01 0x00 0x00 0xb5 0x00 0x00 0x00 0x01 0x00 0x00 0xb6 0x00 0x00 0x00 0x01 0x00 0x00 0xb7 0x00 0x00 0x00 0x01 0x00 0x00 0xb8 0x00 0x00 0x00 0x01 0x00 0x00 0xb9 0x00 0x00 0x00 0x01 0x00 0x00 0xba 0x00 0x00 0x00 0x01 0x00 0x00 0xbb 0x00 0x00 0x00 0x01 0x00 0x00 0xbc 0x00 0x00 0x00 0x01 0x00 0x00 0xbd 0x00 0x00 0x00 0x01 0x00 0x00 0xbe 0x00 0x00 0x00 0x01 0x00 0x00 0xbf 0x00 0x00 0x00 0x01 0x00 0x00>;
};
scp_gpio@105c8000 {
reg = <0x00 0x105c8000 0x00 0x1000>;
compatible = "mediatek,scp_gpio";
};
l2sofifomng@850a8000 {
reg = <0x00 0x850a8000 0x00 0x1000>;
compatible = "mediatek,l2sofifomng";
};
i2c@1100f000 {
phandle = <0x59>;
mediatek,use-open-drain;
reg = <0x00 0x1100f000 0x00 0x1000 0x00 0x11000400 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x0e 0x15 0x2b>;
interrupts = <0x00 0x54 0x08>;
id = <0x03>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
nfc@08 {
phandle = <0x12c>;
reg = <0x08>;
status = "okay";
compatible = "mediatek,nfc";
};
it66121_addr@4c {
reg = <0x4c>;
compatible = "ite,it66121-i2c";
};
};
sramrom@10214000 {
reg = <0x00 0x10214000 0x00 0x1000>;
compatible = "mediatek,sramrom";
};
reserved-memory {
phandle = <0x51>;
ranges;
#size-cells = <0x02>;
#address-cells = <0x02>;
mblock-11-minirdump {
no-map;
reg = <0x00 0x544f0000 0x00 0x10000>;
compatible = "mediatek,minirdump";
};
mblock-5-atf-log-reserved {
no-map;
reg = <0x00 0xbfe00000 0x00 0x40000>;
compatible = "mediatek,atf-log-reserved";
};
zone-movable-cma-memory {
size = <0x00 0xffc00000>;
compatible = "mediatek,zone_movable_cma";
alloc-ranges = <0x00 0xc0000000 0x01 0x00>;
alignment = <0x00 0x10000000>;
};
mblock-3-log_store {
reg = <0x00 0x7ffc0000 0x00 0x40000>;
compatible = "mediatek,log_store";
};
mblock-4-atf-reserved {
no-map;
reg = <0x00 0x54600000 0x00 0x40000>;
compatible = "mediatek,atf-reserved";
};
reserve-memory-dram_r0_dummy_read {
size = <0x00 0x1000>;
compatible = "reserve-memory-dram_r0_dummy_read";
alloc-ranges = <0x00 0x5e900000 0x00 0x196f0000>;
alignment = <0x00 0x1000>;
};
reserve-memory-sspm_share {
no-map;
status = <0x6f6b6179>;
size = <0x00 0x510000>;
compatible = "mediatek,reserve-memory-sspm_share";
alloc-ranges = <0x00 0x40000000 0x00 0x60000000>;
alignment = <0x00 0x10000>;
};
mblock-7-tee-reserved {
no-map;
reg = <0x00 0x7ec00000 0x00 0x1300000>;
compatible = "mediatek,tee-reserved";
};
zmc-default {
status = "disabled";
size = <0x00 0xffc00000>;
compatible = "mediatek,zone_movable_cma";
alloc-ranges = <0x00 0xc0000000 0x01 0x00>;
alignment = <0x00 0x10000000>;
};
mblock-2-dramc-rk1 {
no-map;
reg = <0x01 0xbffff000 0x00 0x1000>;
compatible = "mediatek,dramc-rk1";
};
mblock-15-SCP-reserved {
no-map;
reg = <0x00 0x9cf00000 0x00 0x600000>;
compatible = "mediatek,SCP-reserved";
};
mblock-9-ram_console {
no-map;
reg = <0x00 0x54400000 0x00 0x10000>;
compatible = "mediatek,ram_console";
};
reserve-memory-dram_r1_dummy_read {
size = <0x00 0x1000>;
compatible = "reserve-memory-dram_r1_dummy_read";
alloc-ranges = <0x00 0xc0000000 0x00 0xfffff000>;
alignment = <0x00 0x1000>;
};
mblock-10-pstore {
no-map;
reg = <0x00 0x54410000 0x00 0xe0000>;
compatible = "mediatek,pstore";
};
mblock-1-dramc-rk0 {
no-map;
reg = <0x00 0xbffff000 0x00 0x1000>;
compatible = "mediatek,dramc-rk0";
};
mblock-14-SPM-reserved {
no-map;
reg = <0x00 0x77ff0000 0x00 0x10000>;
compatible = "mediatek,SPM-reserved";
};
mblock-16-ccci_tag_mem {
reg = <0x00 0x9d5e0000 0x00 0x10000>;
compatible = "mediatek,ccci_tag_mem";
};
mblock-13-vpu_binary {
no-map;
reg = <0x00 0x9d5f0000 0x00 0x2a10000>;
compatible = "mediatek,vpu_binary";
};
consys-reserve-memory {
no-map;
size = <0x00 0x200000>;
compatible = "mediatek,consys-reserve-memory";
alloc-ranges = <0x00 0x40000000 0x00 0x80000000>;
alignment = <0x00 0x200000>;
};
mblock-6-SSPM-reserved {
no-map;
reg = <0x00 0x7ff00000 0x00 0xc0000>;
compatible = "mediatek,SSPM-reserved";
};
mblock-12-framebuffer {
no-map;
reg = <0x00 0x7cae0000 0x00 0x1f20000>;
compatible = "mediatek,framebuffer";
};
reserve-memory-scp_share {
no-map;
size = <0x00 0x1400000>;
compatible = "mediatek,reserve-memory-scp_share";
alloc-ranges = <0x00 0x40000000 0x00 0x50000000>;
alignment = <0x00 0x1000000>;
};
mblock-8-items-reserved {
no-map;
reg = <0x00 0x7ea00000 0x00 0x200000>;
compatible = "mediatek,items-reserved";
};
};
shreg2@83030000 {
reg = <0x00 0x83030000 0x00 0x1000>;
compatible = "mediatek,shreg2";
};
mdp_rdma1@14002000 {
phandle = <0x32>;
reg = <0x00 0x14002000 0x00 0x1000>;
compatible = "mediatek,mdp_rdma1";
interrupts = <0x00 0xdb 0x08>;
};
pmic_clock_buffer_ctrl {
phandle = <0xbd>;
status = "okay";
compatible = "mediatek,pmic_clock_buffer";
mediatek,clkbuf-config = <0x02 0x01 0x00 0x02 0x00 0x00 0x01>;
mediatek,clkbuf-quantity = <0x07>;
mediatek,clkbuf-driving-current = <0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff 0xffffffff>;
};
mt_soc_pcm_voice_usb {
compatible = "mediatek,mt_soc_pcm_voice_usb";
};
mdp_tdshp@14007000 {
phandle = <0x37>;
reg = <0x00 0x14007000 0x00 0x1000>;
compatible = "mediatek,mdp_tdshp";
clocks = <0x2f 0x11>;
interrupts = <0x00 0xde 0x08>;
clock-names = "MDP_TDSHP";
};
psmcu_misc@80200000 {
reg = <0x00 0x80200000 0x00 0x1000>;
compatible = "mediatek,psmcu_misc";
};
l2dlfifomng@850a4000 {
reg = <0x00 0x850a4000 0x00 0x1000>;
compatible = "mediatek,l2dlfifomng";
};
mipi_rx_ana_csi0b@11c81000 {
reg = <0x00 0x11c81000 0x00 0x1000>;
compatible = "mediatek,mipi_rx_ana_csi0b";
};
spi3@11013000 {
mediatek,pad-select = <0x00>;
phandle = <0x9b>;
reg = <0x00 0x11013000 0x00 0x1000>;
compatible = "mediatek,mt6765-spi";
clocks = <0x42 0x37 0x42 0x07 0x15 0x3d>;
interrupts = <0x00 0x82 0x08>;
clock-names = "parent-clk\0sel-clk\0spi-clk";
};
md_ppc_top@803d0000 {
reg = <0x00 0x803d0000 0x00 0x1000>;
compatible = "mediatek,md_ppc_top";
};
psmcu_mbist_config@80240000 {
reg = <0x00 0x80240000 0x00 0x1000>;
compatible = "mediatek,psmcu_mbist_config";
};
mt_soc_voip_bt_in {
compatible = "mediatek,mt_soc_pcm_bt_dai";
};
ipu_adl@19010000 {
phandle = <0xab>;
reg = <0x00 0x19010000 0x00 0x1000>;
compatible = "mediatek,ipu_adl\0syscon";
#clock-cells = <0x01>;
};
mdcldma@10014000 {
phandle = <0x2a>;
reg = <0x00 0x10014000 0x00 0x1000 0x00 0x1021b000 0x00 0x1000 0x00 0x10209000 0x00 0x1000 0x00 0x1020a000 0x00 0x1000>;
mediatek,md_id = <0x00>;
compatible = "mediatek,mdcldma";
clocks = <0x2e 0x01 0x15 0x37 0x15 0x2e 0x15 0x31 0x15 0x26 0x15 0x27 0x15 0x5d 0x15 0x5e>;
interrupts = <0x00 0xad 0x04 0x00 0x97 0x08 0x00 0x98 0x08 0x00 0x11b 0x02>;
clock-names = "scp-sys-md1-main\0infra-cldma-bclk\0infra-ccif-ap\0infra-ccif-md\0infra-ccif1-ap\0infra-ccif1-md\0infra-ccif2-ap\0infra-ccif2-md";
mediatek,cldma_capability = <0x06>;
};
hacc@1000a000 {
reg = <0x00 0x1000a000 0x00 0x1000>;
compatible = "mediatek,hacc";
interrupts = <0x00 0xc3 0x08>;
};
simif2@80050000 {
reg = <0x00 0x80050000 0x00 0x1000>;
compatible = "mediatek,simif2";
};
indec@87810000 {
reg = <0x00 0x87810000 0x00 0x1000>;
compatible = "mediatek,indec";
};
sspm@10440000 {
reg = <0x00 0x10440000 0x00 0x10000 0x00 0x10450000 0x00 0x100 0x00 0x10451000 0x00 0x08 0x00 0x10460000 0x00 0x100 0x00 0x10461000 0x00 0x08 0x00 0x10470000 0x00 0x100 0x00 0x10471000 0x00 0x08 0x00 0x10480000 0x00 0x100 0x00 0x10481000 0x00 0x08 0x00 0x10490000 0x00 0x100 0x00 0x10491000 0x00 0x08>;
interrupt-names = "ipc\0mbox0\0mbox1\0mbox2\0mbox3\0mbox4";
compatible = "mediatek,sspm";
interrupts = <0x00 0xd0 0x04 0x00 0xd3 0x04 0x00 0xd4 0x04 0x00 0xd5 0x04 0x00 0xd6 0x04 0x00 0xd7 0x04>;
reg-names = "cfgreg\0mbox0_base\0mbox0_ctrl\0mbox1_base\0mbox1_ctrl\0mbox2_base\0mbox2_ctrl\0mbox3_base\0mbox3_ctrl\0mbox4_base\0mbox4_ctrl";
};
seninf_top@1a040000 {
reg = <0x00 0x1a040000 0x00 0x1000>;
compatible = "mediatek,seninf_top";
clocks = <0x2e 0x03 0x2e 0x09 0x4a 0x05 0x42 0x1c 0x42 0x05 0x42 0x1e 0x42 0x28 0x42 0x29 0x2c 0x42 0x65 0x42 0x45 0x42 0x64 0x42 0x60 0x42 0x66 0x42 0x67>;
clock-names = "SCP_SYS_DIS\0SCP_SYS_CAM\0CAMSYS_SENINF_CGPDN\0TOP_MUX_SENINF\0TOP_MUX_CAMTG\0TOP_MUX_CAMTG2\0TOP_MUX_CAMTG3\0TOP_MUX_CAMTG4\0TOP_CLK26M\0TOP_UNIVP_192M_D8\0TOP_UNIVPLL_D3_D8\0TOP_UNIVP_192M_D4\0TOP_F26M_CK_D2\0TOP_UNIVP_192M_D16\0TOP_UNIVP_192M_D32";
};
vp8_vld@16026800 {
reg = <0x00 0x16026800 0x00 0x1000>;
compatible = "mediatek,vp8_vld";
};
dwrap0@87890000 {
reg = <0x00 0x87890000 0x00 0x1000>;
compatible = "mediatek,dwrap0";
};
msdc0_top@11f50000 {
reg = <0x00 0x11f50000 0x00 0x1000>;
compatible = "mediatek,msdc0_top";
};
dxcc_sec@10210000 {
reg = <0x00 0x10210000 0x00 0x1000>;
compatible = "mediatek,dxcc_sec";
interrupts = <0x00 0xaa 0x04>;
};
mt_soc_i2s0_awb_pcm {
compatible = "mediatek,mt_soc_pcm_i2s0_awb";
};
iocfg_2@11e70000 {
phandle = <0x21>;
reg = <0x00 0x11e70000 0x00 0x1000>;
compatible = "mediatek,iocfg_2\0syscon";
};
dsi0@14014000 {
reg = <0x00 0x14014000 0x00 0x1000>;
compatible = "mediatek,dsi0";
interrupts = <0x00 0xec 0x08>;
};
dsi_te {
phandle = <0xa8>;
status = "okay";
compatible = "mediatek, DSI_TE-eint";
interrupt-parent = <0x1b>;
interrupts = <0x2c 0x01 0x2c 0x00>;
};
btif@1100c000 {
reg = <0x00 0x1100c000 0x00 0x1000 0x00 0x11000a80 0x00 0x80 0x00 0x11000b00 0x00 0x80>;
compatible = "mediatek,btif";
clocks = <0x15 0x1b 0x15 0x2b>;
interrupts = <0x00 0x72 0x08 0x00 0x8b 0x08 0x00 0x8c 0x08>;
clock-names = "btifc\0apdmac";
};
l2dlhbdma@85030000 {
reg = <0x00 0x85030000 0x00 0x1000>;
compatible = "mediatek,l2dlhbdma";
};
i2c@11017000 {
phandle = <0x5b>;
reg = <0x00 0x11017000 0x00 0x1000 0x00 0x11000580 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x33e140>;
#size-cells = <0x00>;
clocks = <0x15 0x47 0x15 0x2b 0x15 0x46>;
interrupts = <0x00 0x85 0x08>;
id = <0x05>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
mediatek,use-push-pull;
clock-div = <0x05>;
usb_type_c@4e {
phandle = <0x130>;
reg = <0x4e>;
status = "okay";
compatible = "mediatek,usb_type_c";
};
subpmic_pmu@34 {
phandle = <0x131>;
reg = <0x34>;
status = "okay";
compatible = "mediatek,subpmic_pmu";
};
};
md1_abb_mixedsys@8020c000 {
reg = <0x00 0x8020c000 0x00 0x1000>;
compatible = "mediatek,md1_abb_mixedsys";
};
md_uart2@80340000 {
reg = <0x00 0x80340000 0x00 0x1000>;
compatible = "mediatek,md_uart2";
};
seninf4@1a043000 {
reg = <0x00 0x1a043000 0x00 0x1000>;
compatible = "mediatek,seninf4";
};
chipid@08000000 {
reg = <0x00 0x8000000 0x00 0x04 0x00 0x8000004 0x00 0x04 0x00 0x8000008 0x00 0x04 0x00 0x800000c 0x00 0x04>;
compatible = "mediatek,chipid";
};
mdp_wrot0@14005000 {
phandle = <0x35>;
reg = <0x00 0x14005000 0x00 0x1000>;
compatible = "mediatek,mdp_wrot0";
clocks = <0x2f 0x12>;
interrupts = <0x00 0xdf 0x08>;
clock-names = "MDP_WROT0";
};
hseq_dc@87410000 {
reg = <0x00 0x87410000 0x00 0x1000>;
compatible = "mediatek,hseq_dc";
};
i2c@11014000 {
phandle = <0x5f>;
mediatek,use-open-drain;
reg = <0x00 0x11014000 0x00 0x1000 0x00 0x11000180 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x49 0x15 0x2b 0x15 0x48>;
interrupts = <0x00 0x83 0x08>;
id = <0x09>;
clock-names = "main\0dma\0arb";
#address-cells = <0x01>;
clock-div = <0x05>;
};
a7_mbist_config@f0410000 {
reg = <0x00 0xf0410000 0x00 0x1000>;
compatible = "mediatek,a7_mbist_config";
};
mt_charger {
phandle = <0xb3>;
compatible = "mediatek,mt-charger";
};
memory {
reg = <0x00 0x40000000 0x01 0x80000000>;
items_reserved_mem = <0xa07e 0x00 0x2000 0x00>;
mblock_info = <0xe000000 0x00 0x40 0x00 0x800 0x00 0x00 0x00 0x884c 0x00 0x7807 0x00 0x00 0x00 0x854 0x00 0x3800 0x00 0x00 0x00 0x5054 0x00 0x1000 0x00 0x00 0x00 0x6454 0x00 0x1c00 0x00 0x00 0x00 0xa054 0x00 0x6000 0x00 0x00 0x00 0x4056 0x00 0x5000 0x00 0x00 0x00 0x905e 0x00 0x6f19 0x00 0x00 0x00 0x78 0x00 0x6e04 0x00 0x00 0x00 0x80 0x00 0xf01c 0x00 0x00 0x00 0x509d 0x00 0xe00 0x00 0x00 0x00 0xa0 0x00 0xe01f 0x00 0x00 0x00 0xe4bf 0x00 0xf01b00 0x00 0x00 0x00 0xc0 0x00 0xf0ffff 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x99999999 0x2000000 0x17000000 0x00 0xf0ffbf 0x00 0x100000 0x00 0x00 0x6472616d 0x632d726b 0x30006472 0x616d632d 0x726b3100 0x6472616d 0x632d726b 0x32006472 0x616d632d 0x726b3300 0x5b455252 0x4f525d20 0x30782578 0x3a0a0020 0x20206d6f 0x64756c65 0x20202020 0x3a203078 0x25780a00 0x2020206c 0x6576656c 0x315f6572 0x723a2030 0x7825780a 0x202020 0x6c657665 0x6c325f65 0x72723a20 0x30782578 0xa002573 0x203a2075 0x73622072 0x00 0xf0ffbf 0x1000000 0x100000 0x00 0x00 0x6472616d 0x632d726b 0x31006472 0x616d632d 0x726b3200 0x6472616d 0x632d726b 0x33005b45 0x52524f52 0x5d203078 0x25783a0a 0x202020 0x6d6f6475 0x6c652020 0x20203a20 0x30782578 0xa002020 0x206c6576 0x656c315f 0x6572723a 0x20307825 0x780a0020 0x20206c65 0x76656c32 0x5f657272 0x3a203078 0x25780a00 0x2573203a 0x20757362 0x20726563 0x65697665 0x2074696d 0x00 0xfc7f 0x00 0x400 0x00 0x1000000 0x6c6f675f 0x73746f72 0x65002573 0x3a647261 0x6d206c6f 0x6720616c 0x6c6f6361 0x74696f6e 0x20657272 0x6f72210a 0x25733a 0x7372616d 0x5f686561 0x64657220 0x30782578 0x2c736967 0x20307825 0x782c2073 0x72616d5f 0x6472616d 0x5f627566 0x66203078 0x25782c20 0x6275665f 0x61646472 0x20307825 0x780a0025 0x733a2064 0x72616d20 0x62756666 0x2066756c 0x6c005b42 0x00 0x6054 0x00 0x400 0x00 0x00 0x6174662d 0x72657365 0x72766564 0x617466 0x5f647261 0x6d5f7265 0x733a3078 0x25782c20 0x73686f75 0x6c643a30 0x7825782c 0x20617373 0x65727421 0xa002f6d 0x6e742f68 0x64332f6c 0x7771322f 0x31302e30 0x2f71305f 0x6d70315f 0x322f616c 0x70732f76 0x656e646f 0x722f6d65 0x64696174 0x656b2f70 0x726f7072 0x69657461 0x72792f62 0x6f6f7461 0x626c652f 0x626f6f74 0x00 0xe0bf 0x00 0x400 0x00 0x00 0x6174662d 0x6c6f672d 0x72657365 0x72766564 0x257320 0x4661696c 0x20746f20 0x67657420 0x73656375 0x7265206d 0x656d6f72 0x79206164 0x64726573 0x730a0025 0x73205b42 0x5d535241 0x4d524f4d 0x20534543 0x5f414444 0x523a3078 0x25782c20 0x5345435f 0x41444452 0x313a3078 0x25782c20 0x5345435f 0x41444452 0x323a3078 0x25780a00 0x5b545a5f 0x5345435f 0x4346475d 0x00 0xf07f 0x00 0xc00 0x00 0x00 0x5353504d 0x2d726573 0x65727665 0x64002573 0x20535350 0x4d207061 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0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
orig_dram_info = <0x2000000 0x00 0x40 0x00 0x80 0x00 0xc0 0x00 0x00 0x1000000 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00>;
device_type = "memory";
lca_reserved_mem = <0x00 0x00 0x00 0x00>;
tee_reserved_mem = <0xe0bf 0x00 0x400 0x00>;
};
rsc@15029000 {
reg = <0x00 0x15029000 0x00 0x1000>;
compatible = "mediatek,rsc";
clocks = <0x49 0x05>;
interrupts = <0x00 0x10f 0x08>;
clock-names = "RSC_CLK_IMG_RSC";
};
mdcldmamisc@1021c800 {
reg = <0x00 0x1021c800 0x00 0x1000>;
compatible = "mediatek,mdcldmamisc";
};
mdm_psys_misc@8020d000 {
reg = <0x00 0x8020d000 0x00 0x1000>;
compatible = "mediatek,mdm_psys_misc";
};
gauge_timer {
compatible = "mediatek,gauge_timer_service";
};
radio_md_cfg {
phandle = <0xb1>;
compatible = "mediatek,radio_md_cfg";
};
iocfg_1@11e80000 {
phandle = <0x20>;
reg = <0x00 0x11e80000 0x00 0x1000>;
compatible = "mediatek,iocfg_1\0syscon";
};
mt6358_gauge {
alias_name = "MT6358";
compatible = "mediatek,mt6358_gauge";
gauge_name = "gauge";
};
audio@11220000 {
phandle = <0x3d>;
reg = <0x00 0x11220000 0x00 0x1000>;
compatible = "mediatek,audio\0syscon";
#clock-cells = <0x01>;
mediatek,btcvsd_snd = <0x45>;
};
md_ccif0@1020a000 {
reg = <0x00 0x1020a000 0x00 0x1000>;
compatible = "mediatek,md_ccif0";
};
uea_uia_u0@87600000 {
reg = <0x00 0x87600000 0x00 0x1000>;
compatible = "mediatek,uea_uia_u0";
};
fdvt_dma@1502b000 {
reg = <0x00 0x1502b000 0x00 0x1000>;
compatible = "mediatek,fdvt_dma";
};
i2c@11011000 {
phandle = <0x57>;
mediatek,use-open-drain;
mediatek,skip_scp_sema;
reg = <0x00 0x11011000 0x00 0x1000 0x00 0x11000480 0x00 0x80>;
compatible = "mediatek,i2c";
mediatek,hs_only;
clock-frequency = <0x61a80>;
#size-cells = <0x00>;
clocks = <0x15 0x3a 0x15 0x2b>;
interrupts = <0x00 0x55 0x08>;
id = <0x01>;
clock-names = "main\0dma";
#address-cells = <0x01>;
clock-div = <0x05>;
msensor@30 {
mmc3416x_addr = <0x30 0x00 0x00 0x00>;
reg = <0x30>;
status = "okay";
mmc3630x_direction = <0x02>;
compatible = "mediatek,msensor";
is_batch_supported = <0x00>;
mmc3630x_addr = <0x30 0x00 0x00 0x00>;
mmc3416x_direction = <0x02>;
i2c_num = <0x02>;
power_id = <0xffff>;
power_vol = <0x00>;
};
alsps@49 {
stk3x1x_thld_low = <0x5dc>;
polling_mode_als = <0x01>;
stk3x3x_value = <0x00 0x50 0xa0 0x104 0x1c2 0x258 0x2ee 0x3e8 0x4e2 0x5aa 0x6a4 0xa28 0xce4 0x1400 0x1e00 0x2800>;
stk3x3x_level = <0x0a 0x50 0xa0 0xf0 0x190 0x230 0x2bc 0x384 0x44c 0x514 0x5dc 0x93c 0xbb8 0x122f 0x1b46>;
stk3x1x_addr = <0x48 0x00 0x00 0x00>;
stk3x3x_thld_low = <0x5dc>;
reg = <0x49>;
stk3x1x_value = <0x1e 0x28 0x50 0x82 0xb4 0x122 0x1c2 0x258 0x44c 0x744 0x9c4 0xd48 0x1450 0x2800 0x2800 0x2800>;
is_batch_supported_ps = <0x00>;
stk3x1x_level = <0x05 0x09 0x24 0x3b 0x52 0x84 0xcd 0x111 0x1f4 0x34d 0x470 0x609 0x93c 0x122f 0x1b46>;
status = "okay";
pinctrl-1 = <0xe4>;
compatible = "mediatek,alsps";
firlen = <0x10>;
is_batch_supported = <0x00>;
interrupt-parent = <0x1b>;
i2c_num = <0x01>;
power_id = <0xffff>;
epl259x_addr = <0x49 0x00 0x00 0x00>;
interrupts = <0x06 0x08 0x06 0x00>;
stk3x3x_addr = <0x57 0x00 0x00 0x00>;
stk3x1x_thld_high = <0x6a4>;
polling_mode_ps = <0x00>;
epl259x_thld_high = <0x320>;
is_batch_supported_als = <0x00>;
pinctrl-0 = <0xe3>;
stk3x3x_thld_high = <0x6a4>;
power_vol = <0x00>;
epl259x_thld_low = <0x1f4>;
epl259x_value = <0x0a 0x1e 0x3c 0x50 0x64 0xc8 0x190 0x258 0x320 0x5dc 0xbb8 0x1770 0x2710 0x4e20 0x9c40 0xea60>;
epl259x_level = <0x14 0x2d 0x46 0x5a 0x96 0x12c 0x1f4 0x2bc 0x47e 0x8ca 0x1194 0x1f40 0x3a98 0x7530 0xc350>;
pinctrl-names = "pin_default\0pin_cfg";
debounce = <0x06 0x00>;
};
gsensor@18 {
mc34xx_addr = <0x4c 0x00 0x00 0x00>;
stk8baxx_direction = <0x03>;
reg = <0x18>;
status = "okay";
mpu6050g_direction = <0x00>;
compatible = "mediatek,gsensor";
firlen = <0x10>;
is_batch_supported = <0x00>;
icm426xx_a_addr = <0x68 0x00 0x00 0x00>;
bma222e_addr = <0x18 0x00 0x00 0x00>;
bma222e_direction = <0x00>;
icm426xx_a_direction = <0x00>;
i2c_num = <0x02>;
power_id = <0xffff>;
power_vol = <0x00>;
mpu6050g_addr = <0x68 0x00 0x00 0x00>;
mc34xx_direction = <0x00>;
stk8baxx_addr = <0x18 0x00 0x00 0x00>;
};
gyro@68 {
icm426xx_g_direction = <0x00>;
reg = <0x68>;
status = "okay";
compatible = "mediatek,gyro";
firlen = <0x00>;
icm426xx_g_addr = <0x68 0x00 0x00 0x00>;
is_batch_supported = <0x00>;
i2c_num = <0x02>;
power_id = <0xffff>;
mpu6050gy_addr = <0x68 0x00 0x00 0x00>;
mpu6050gy_direction = <0x00>;
power_vol = <0x00>;
};
};
utos {
compatible = "microtrust,utos";
interrupts = <0x00 0x128 0x01 0x00 0x129 0x01>;
};
l2ulfifomng@850a0000 {
reg = <0x00 0x850a0000 0x00 0x1000>;
compatible = "mediatek,l2ulfifomng";
};
md_debug2@80090000 {
reg = <0x00 0x80090000 0x00 0x1000>;
compatible = "mediatek,md_debug2";
};
dip4@15025000 {
reg = <0x00 0x15025000 0x00 0x1000>;
compatible = "mediatek,dip4";
};
ssusb_ip_sleep {
phandle = <0xc9>;
status = "okay";
compatible = "mediatek,usb_ipsleep";
interrupt-parent = <0x1b>;
interrupts = <0xb3 0x08 0xbb 0x00>;
};
consys@18070000 {
phandle = <0x29>;
reg = <0x00 0x18070000 0x00 0x1000 0x00 0x10007000 0x00 0x100 0x00 0x10001000 0x00 0x1000 0x00 0x10006000 0x00 0x1000>;
status = "okay";
pinctrl-1 = <0xe0>;
compatible = "mediatek,mt6771-consys";
pinctrl-3 = <0xe2>;
clocks = <0x2e 0x02>;
interrupts = <0x00 0x121 0x08 0x00 0x123 0x08>;
clock-names = "conn";
pinctrl-0 = <0xdf>;
pinctrl-2 = <0xe1>;
pinctrl-names = "default\0gps_lna_state_init\0gps_lna_state_oh\0gps_lna_state_ol";
};
};
Any ideas ? Is there a way to pack boot.img so fastboot can boot it ?
New kernel scheduler in Linux 6.6
from omgubuntu.co.uk:
One of the most notable new features in Linux 6.6 is the EEVDF scheduler, which replaces the CFS scheduler.
EEVDF fulfils the same role as CFS, helping divides CPU time between processes – but does so more efficiently, with less lag, and reduced latency. However, kernel devs caution the new schedule may, in rare cases, cause performance regressions with specific workloads – but it’ll be fixed in time.
It’ll be interesting to see benchmarks pitting EEVDF vs CFS. Performance boosts (however minor) are always welcome, and this change sounds like it could provide appreciable boosts in general, as well as for gaming and other latency-sensitive workloads run on Linux.
There’s also a new eventfs subsystem to improve memory efficiency in the tracing subsystem.
Can we use this to speed up the Chromebook kernel?
kukui_bookworm_image root password
Hi, booting from usb OK,
but can't login
root
changeme
Appritiate your help.
Kernel support for Sony PS3 & PS4 joystick/controllers
Would you please add in kernel support for Sony PS3 & PS4 joystick/controllers (Maybe some other popular ones too) in the next mt8 kernel/image?
This seems a useful reference: https://wiki.gentoo.org/wiki/Sony_DualShock
This is for running retropie which seems to run ok on my kukui cb, but lacks the support for the controllers.
I'm currently building a custom kernel on 6.1.51 with the options enabled as per the gentoo wiki, although I'm not a kernel build expert and its currently compiling. Will report back on any success.
Would be nice to have it in there for everyone if it works on arm64.
chromebook_kukui: misc: video decoding/encoding fix for kukui
Hello Hexdump0815,
I found some info about a video decoding/encoding fix. Somehow, postmarketOS guys fixed it!
Here is the kernel patch. It is for postmarketOS kernel v6.1.28.
Thanks,
Aneesh
[Request] Look into the gpu driver for the Acer Chromebook R13 that is in chromeos source tree
I struggled to install linux on my chromebook and tried compiling my own kernel without success until I stumbled upon your project, so thanks a lot.
During my research I also found this: https://elinux.org/User:Uli/Acer_Chromebook_R13_GPU_test_system
Which led me to find the place where the driver is located
Here : https://chromium.googlesource.com/chromiumos/third_party/kernel/+/refs/heads/chromeos-5.4/drivers/gpu/drm/img-rogue/
I have no idea how easy/hard it would be to include in your kernel builds, but maybe it is useful to keep for someday.
Problems with LTS and Linux Stable
Hi,
Just here to give a quick warning that there's some odd regression in Linux stable that appears to break USB booting from my testing on Kukui. This issue is not specific to any filesystem or Linux distribution. I was able to confirm this regression with the Linux stable 6.6.7 release. Booting fails entirely with a load of "Buffer I/O error" messages as well as "lost sync page write" but I do recall USB booting working properly with Linux 6.1 LTS though. It looks like on Linux stable is it either corrupting and/or failing to read contents correctly. I should clarify that I used your patches with Linux stable.
kernel: Unknown kernel command line parameters "cros_secure"
maybe here its more related than on imagebuilder repo
How to fix Bluetooth on other kernels
I got Arch linux running on my kappa with mainline kernel (linux-aarch64). I downloaded the extra files folder and copied them, that fixed wifi and sound. Now, I would like to contribute to the mainline Arch kernel with a Bluetooth patch for mt8183. If you can write a small document about the patches and how to patch a kernel, that would be awesome!
Thanks,
Aneesh
Hello hexdump0815 i would like to get in contact with you Because I would like to ask you how were you made a special image data for Samsung Galaxy Book Go to boot on it debian arm distribution
How do I upgrade the kernel without reflashing?
Hey Hexdump!
Is there any way to upgrade the kernel without reflashing a new image
An observation
I saw a comment by Mrchromebox regarding how to get rw legacy firmware. It involves cbfstool and removing and adding another payload (edk2) to the image. SInce I saw a RW_LEGACY partition when booting into Debian, installing gnome-disk-utility, and seeing the partitions with it. So, probably, we could make some firmware for the boards (kukui, etc.) and flash it. It should be safe since it is RW_LEGACY and not the whole chip being flashed. The problem comes to building EDK2. We'll need to build a custom image, by porting edk2 and the required acpi tables. Or we could try our luck on generic arm64. The problem with that way is that I don't know how to build a generic image, since you can only build for ARM SBCs. And also, here is the comment.
chromebook_kukui: problem: v6.7 or higher, booting pregess is stuck at this line: failed to start systemd-logind.
board: katsu.
using the kconfig config.mt8-6.6.9-stb-mt8+.
As it failed to enter the system, I don't know how to cat the log because I can't use systemctl status.
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