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udma_core

ufs-tool

The UFS Tool project have been created to allow access UFS device from user space, and perform basic set of UFS operations: Read and write UFS device configuration (flags, attributes, descriptors), FFU, etc... The set of UFS Tool features is co-existing and updated beside BSG and SG infrastructure in Linux Kernel.

unity

uos-embedded

Embedded operating system for MIPS, ARM, AVR, MSP430 and i386 architectures

usb20dev

USB 2.0 FS Device controller IP core written in SystemVerilog

usbcore

USB Full-Speed/Hi-Speed Device Controller core for FPGA

usbhost

Simple FIFO-based USB Host Controller

usbhwthinclient4vm

Attempt to attach display/mouse/keyboard to VMWAVE virtual machine. HW device for this: Altera MAX10 FPGA dev kit "marsohod3"

uscscan

usd-s3-resolver

S3 Asset Resolver plugin for Pixar's USD

usrp_marine_radar

Firmware build for use of ettus.com's USRP-1 as a digitizer for pulsed marine radar

ustc-rvsoc

基于 FPGA 的 RISC-V CPU + SoC

uvm

Standard Universal Verification Methodology

uw-appnotes

UW Application Notes

vagrant-memex

DARPA MEMEX project Vagrant VM

ventilator_gui

ventilatorsoftware

Common repo for all ventilator software

verilog-axis

Verilog AXI stream components

verilog-cam

Verilog Content Addressable Memory Module

verilog-dsp

Verilog digital signal processing components

verilog-ethernet

Verilog Ethernet components

verilog-i2c

Verilog I2C

verilog-probe

A very small and simple debug probe designed to be very easy to interface with and be usable via SPI, JTAG and UART.

verilog-uart

Verilog UART

verilog-wishbone

Verilog wishbone components

vhdci_carrier

vhdl-project

Austin, Joe, Clay VHDL Final Project - PCM Encoder/Decoder

virgilio

Your new Mentor for Data Science E-Learning.

vm80a

i8080 precise replica in Verilog, based on reverse engineering of real die

vna