RTL code of some arbitration algorithms which are able to synthesize. I tried to synthesize on Quartus II, a software of Altera for FPGA.

RTL list

1. Absolute Fixed Priority Arbiter

ArbFixedPriorityAbs.v

2. Non-Absolute Fixed Priority Arbiter

ArbFixedPriorityNAbs.v

3. Non-Absolute Fixed Priority Arbiter with LOCK function

ArbFixedPriorityLocked.v

4. Dynamic priority arbiter

ArbDynamicPriority.v

5. Simple Round Robin with a counter

ArbSimpleRR.v

6. Round Robin arbiter with Priority logic

ArbPriorityRR.v

7. Balance Round Robin

ArbBalanceRR.v

Detail Description

http://nguyenquanicd.blogspot.com/search/label/Arbiter?&max-results=5

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