This project is a cache simulator associated with Pintools. It is currently developped at Uppsala University in the UART group for quick evaluation of different strategies for data placement specially with hybrid cache architecture where the cache is divided into several regions with different memory technologies

This framework is made for:

• Evaluation of predictors for hybrid SRAM/NVM cache architecture
• Evaluation of cache replacement/insertion policies
• Evaluation of prefetching strategies
• Evaluation of dead block prediction strategies

The zlib development packages are required for the project. Then the project can simply be compiled with make

cd <path to your cache-simulator.git clone>
make

We need memory traces to feed the simulator. 2 formats are now supported and a precise description can be found in the Memory Wrapper class file.

• Compressed memory traces using the zlib library (traces that are understandable by the compiler can be generated by a pintool script in the Utils directory)
• Text memory traces for debugging purposes

• traces-pintools : it contains a pintools script to generate compressed memory traces
• energy_modeling: contains python scripts to compute the energy consumption and the performance of the cache simulation (based on CACTI/NVsim modeling tools)