Description: Design a simplified version of a MIPS machine and write Verilog programs that describe its structure and simulate its functioning. Use structural (gate level) modeling for all components unless otherwise specified. The machine should include the following components:

1. General purpose registers (register file): 4 registers, 16-bit long, numbered 0 - 3. Register $0 must contain 0 (read-only). Implemented by D flip-flops with gate-level modeling.
2. Other registers: 16-bit program counter, pipeline registers. Implemented by reg vectors in Verilog.
3. Istruction Memory. Word size: 16 bits, word addressed, size: 1024 bytes. Implemented by reg vectors in Verilog.
4. Data Memory. Word size: 16 bits, byte addressed, size: 1024 bytes. Implemented by reg vectors in Verilog.
5. Data Cache (optional): direct mapped, write-through, 16-bit block size, size: 8 blocks. Any kind of Verilog model accepted.
6. ALU: 16-bit data, 3-bit control. Functions: and, or, add, sub, slt.
7. Control unit: may be implemented by behavioral modeling.
8. Other components necessary to connect the main components: multiplexes and decoders implemented by gate-level modeling.

Instruction formats:

R-format (add, sub, and, or, slt)

I-format (addi, lw, sw, beq, bne)

Restrictions:

1. Use structural (gate level) modeling for all components except for the program counter, memories, and pipeline registers.
2. Implement a pipelined datapath and control.