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Thanks for the answer! I think i will try the older one first...
from prudaq.
Can I start and stop the sampling by pull P9_25 low/high?
Is that the right way to do it?
from prudaq.
from prudaq.
Actually the firmware should stop sampling. So it should start and stop sampling from within my c++ programm. Not shure whether there is a file somewhere I can echo to? ( maybe /sys/devices/virtual/misc/beaglelogic/state ? )
Thanks a lot for your advice!
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from prudaq.
Yes, you are right! On the beagleLogic-github page there is a description of the sysfs-attributes (https://github.com/abhishek-kakkar/BeagleLogic/wiki/sysfs-attributes-Reference) and there it says at 'triggerflags':
"If data is not removed fast enough as it arrieved, it may be overwritten. Kernel logs can reveal where the overrun had occurred."
So I randomly tryed the dmesg-command and the nice thing is: it does not only inform you about an overun: every time you read from /dev/beaglelogic
(hexdump -d /dev/beaglelogic |head , or dd if=/dev/beaglelogic of=myfile.bin bs=1M count=64) , dmesg says "capture started with ..." and when the read is finished dmesg says "capture session ended".
So to stop sampling pulling P9_25 high is not necessary. You can simply start and stop reading from /dev/beaglelogic.
Thank you for the advice!
(Btw, the /sys/devices/virtual/misc/beaglelogic/state attribute is for testing purposes only)
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This project is so cool =D
PRU1 waits for a rising or falling edge of the ADC-clock , than samples the ADC output pins. (The pru1 assembler code is also very interesting)
So am I correct in assuming that the beagleLogic samplerate-parameter is actually without function for the PRUDAQ project?
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