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Test: Link

Demo video (broken):

Currently mixer clock is always set to maximum, which affects power consumption.
Also in certain conditions mixer can produce damaged output.

How to play with pixel clock (can potentially damage the hardware, don't try if you're not ready to lose it):
Pixel clock divider control registers are located at 0x100000C address

Bits:

• bits 3-0 - Mixer 0 divider
• bits 7-4 - Mixer 1 divider

Values:

• 0 - base freq / 1
• 1 - base freq / 2

and so on

Bash example (divide base freq by 4. On OPI3 it does mean 600Mhz/4 = 150MHz):

devmem 0x100000C 32 0x3

It's safe to reduce mixer clock (MClk) down to pixel clock (PClk) once hardware down-scaling isn't used
Up-scaling does not require clocking the module faster than pixel clock.

Down-scaling has some limitation (Tested with RGBA8888):

Vertical VI downscaling up to 2x require MClk=2*PClk
Vertical VI downscaling up to 16x require MClk=4*PClk
Horizontal VI downscaling up to 4x require MClk=2*PClk
Horizontal VI downscaling up to 8x require MClk=4*PClk
Horizontal VI downscaling up to 16x require MClk=4*PClk
(TODO: Distinguish between fine/coarse modes)

Vertical UI downscaling up to 2x require MClk=2*PClk
Vertical UI downscaling up to 4x require MClk=4*PClk
Vertical UI downscaling up to 8x require MClk=8*PClk !!!
Vertical UI downscaling up to 16x require MClk=24*PClk !!!
Horizontal UI downscaling up to 4x require MClk=2*PClk
Horizontal UI downscaling up to 8x require MClk=4*PClk

Exceeding these values will cause damaged picture output and in some cases pipeline can freeze.

Power consumption measurements:

• H6 SOC, 1920x1080@60 mode (PClk=148.5MHz, single-plane FB console case)
  Without changing the mixer clock (600MHz): 0.38A
  After changing the mixer clock (150MHz): 0.36A

• H6 SOC, 640x480@60 mode (PClk=25.2MHz, modetest test pattern case)
  Without vhanging the mixer clock (600MHz) 0.35A
  After changing the mixer clock (37.5MHz): 0.33A

Stress testing to ensure it's safe to switch the divider while mixer is doing the work:

while true ; do devmem 0x100000c 4 0x1 ; devmem 0x100000c 4 0x0 ; done

1. Most bottom layer alpha doesn't work
   Test source code: Link

2. Multi-stage blending result is invalid
   Test source code: Link