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Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

License: BSD 2-Clause "Simplified" License

VHDL 5.27% Verilog 93.83% Tcl 0.90%
vhdl verilog synthesis digital-design rtl scripts tcl polito booth-multiplier register-file

vhdl-designsynthesis's Introduction

print("Hello World!")

I'm Gabriel Ganzer (he/him/his), a computer engineer from São Paulo, Brazil. Currently, I'm a Software Developer at Kryptus EED S.A. working with machine learning algorithms and MLOps.

During my spare time, I like to practice Yoga, cook delicious meals, travel, and advocate for LGBTQ+ people! 🏳️‍🌈

Visit my portfolio to learn more about me and get in touch, or check out some of my projects here.

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