Issue

I am failing to reuse the verilog which was generated as litex SoC in my amaranth HDL project. I am able to get it to synthesize, however the Intel Quartus output shows many lines like

object "..." assigned a value but never read

or

Synthesized away node ...

The whole project only consumes 29 LUTs at the end and obviously does not contain the litex SoC.

What is wrong with my setup?
I am currently not able to figure out which of the build output messages contains the hint how to resolve it.

Background

I am working on the project https://github.com/hansfbaier/adat-usb2-audio-interface/ which already consists of the needed gateware to run a USB Audio interface. I would like to include a litex SoC to add some additional control logic, which is too resource-intensive to implement in the gateware.

I feel this unwritten wiki page would be exactly what I need:
https://github.com/enjoy-digital/litex/wiki/Export-Your-Core-SoC-To-Verilog

What I did

1. Build a plain litex SoC for now: python3 -m litex_boards.targets.qmtech_5cefa2 --build --load according to the documentation
2. Obtain the build files and place them in my amaranth project: VexRiscv.v, qmtech_5cefa2.v, qmtech_5cefa2_mem.init, qmtech_5cefa2_rom.init, qmtech_5cefa2_sram.init
3. Write an amaranth module litex_soc.py which creates an Instance() of the litex SoC.
4. Add this module to my code: https://github.com/fritzbauer/litex_instance/blob/master/instance_example.py#L23

Troubleshooting Resources

• The build output can be found in this repository's build.log
• The generated verilog can be found in this repository's build.v
• The full build folder content has been attached to this issue: build.zip