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ghidra-xtensa-flix's Introduction

Installation

$ cd ghidra_10.1.5_PUBLIC/Ghidra/Processors
$ git clone https://github.com/flto/ghidra-xtensa-flix Xtensa
$ cd Xtensa
$ make
$

Notes

  • See XXX/TODO comments in xtensaFLIX.sinc
  • Hardware loops don't always decompile correctly (only small loops with fixed iterations work?)

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yath avatar ebiroll avatar shuffle2 avatar flto avatar iridiumxor avatar icewind1991 avatar

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ghidra-xtensa-flix's Issues

Instruction decoding

Hi,
Its not an issue in your code, but just an question about your approach. So seems that Xtensa provided ISA for their basic instruction set, but there is no information how the FLIX instructions should be decoded. So some basic stuff remain the same as the instruction opcode, however some parts differs. For example the instruction opcode instead of being prefixed with 0xfe-0xff it got shifted into end of the instruction within the slot. The other not obvious example from your code is EXTUI instruction in slot0. You described it as:

slot0:"extui" s0_at, Ws0_ar, s0_sh, s0_mask is s0_op = 0 & s0_op2lh = 0b010 & s0_sh & s0_mask & Ws0_ar & s0_at {
    local shifted:4 = s0_at >> s0_sh;
    local mask:4 = (1:4 << (s0_mask + 1))-1;
    Ws0_ar = shifted & mask;
}

So according to EXTUI description in ISA would assume format like EXTUI ar, at, shiftimm, maskimm but you swap at and ar registers. Therefore, could you explain your approach? Or could you share any documentation you followed to take that decisions?

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