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siphash's Introduction

Basic+SSE2+SSSE3 implementation of SipHash-2-4 based off the paper. On an E5200, icc gives the best speeds for all SSE versions & 32bit versions, gcc gives the best speed for 64bit basic

done to see how difficult implementing the spec was as their source is not up (yet), and curious about 32bit performance

Performance on an E5200

Best Impl.7 bytes128 bytes1024 bytes
icc 32bit202 cycles1015 cycles6.7 cpb
icc 32bit sse2135 cycles688 cycles4.48 cpb
icc 32bit ssse3125 cycles614 cycles3.98 cpb
gcc 64bit61 cycles276 cycles1.81 cpb

License

Public Domain

siphash's People

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floodyberry avatar paulharris avatar

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siphash's Issues

Test does not cover len=1024

in test.c, shouldn't the loop read:

for (len = 1; len <= 1024; len++) {

instead of:

for (len = 1; len < 1024; len++) {

?

`rdtsc` may be reorderd by an out of order CPU

This code looks wrong:

        __asm__ __volatile__("rdtsc" : "=a" (lo), "=d" (hi));

Snippet from this paper http://download.intel.com/embedded/software/IA/324264.pdf :

Starting with the Intel Pentium processor, most Intel CPUs support out-of-order execution of the code. The purpose is to optimize the penalties due to the different instruction latencies. Unfortunately this feature does not guarantee that the temporal sequence of the single compiled C instructions will respect the sequence of the instruction themselves as written in the source C file. When we call the RDTSC instruction, we pretend that that instruction will be executed exactly at the beginning and at the end of code being measured (i.e., we don’t want to measure compiled code executed outside of the RDTSC calls or executed in between the calls themselves).

Possible a duplicate

I found this lines in sse2 and ssse3 sipcompress macro implementation:

v13 = _mm_unpacklo_epi64(v11, v33);
v13 = _mm_unpacklo_epi64(v11, v33); \

Looks like its make no sense to write it twice. So it's just a typo or I can't understand something?

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