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Home Page: https://www.faradayrf.com
License: Other
Faraday hardware design files
Home Page: https://www.faradayrf.com
License: Other
Unecessary mousebites with PCB:NG because they automatically place their own for tab routing on a panel. They will use the spots for their own mousebites once I remove them. Following this, I won't need to combine the drill files either since all holes will be plated.
which appears to hge an editting remnant
Perhaps in addition to removing it, add a .gitignore rule
We decided that while the power supply of Rev C is awesome! This is a board that will be produced in large quantities and we don't need this much complexity.
Create standard panels with Faraday on them to reduce manufacturing costs, increase build efficiency, and increase yield.
Most work shall be completed in the Production branch until it is ordered, then it will be moved over to Master.
When trying to upload the kicad_pcb file directly to macrofab to get quotes, the parser would fail. Thanks to their help it was identified as a single quote around line 7,288 in
Commit: 0bd3c28
Error
(gr_text "0.063\" +- 10%" (at 294.64 127.762) (layer Dwgs.User)
(effects (font (size 1.5 1.5) (thickness 0.3)))
This text is on my drawings layer for the PCB stackup. It appears that the escape used for the quote isn't dealt with nicely in the parser.
A full blown datasheet is not necessary at this point, but a single table to reference for the standard operating parameters of the board would be helpful.
Check that locations are correct and make sense. PCB:NG may not need mousebites predefined but it helps them even if they don't use my exact design.
Check Rev C Gerbers against Rev B Gerbers to make sure any and all differences are accounted for. The quickest way to do this is to use GerbV to XOR Rev B and Rev C, leaving the differences highlighted.
Test the CC430's ability to operate with these capacitors DNP'd.
The GPS is a prime spot to remove components from. We may not actually need the 900MHz RF protection ferrites and capacitors.
Inductors
Capacitors
Testing in Hardware on Rev B
Basic testing of removing these parts or shorting around them and verifying that when transmitting the GPS remains locked is a good real-world test.
Check Rev C Gerbers against Rev B Gerbers to make sure any and all differences are accounted for. The quickest way to do this is to use GerbV to XOR Rev B and Rev C, leaving the differences highlighted.
I needed to change the gerbers to account for Advanced Circuits stackup which changed the 50 Ohm and 100 Ohm traces as well as forced the pullback of some copper ground planes. I also noticed that I had to change a few via's back to 13 mil holes but that didn't show up on the last attempt. Wierd.
The button has rarely seen actual use and the second LED is nice but maybe we could DNP it or remove it entirely.
Haha... R2 and D2 are the LED 2 components... oh it's the small things ๐
Ensure orientation makes sense. Verify library IPC pin 1 orientation and ensure output file makes sense to rotation file. I have used this blog post from Tom Hausherr at Mentor Graphics as a guideline for my library management process.
IPC-7351B Zero Rotation means that two pin passives always have zero rotation with pin 1 on the left, diodes have pin 1 (cathode) on the left. IC packages always have zero rotation pin 1 located in upper left quadrant. This standard allows the assembler to relate tape and reel orientation to PCB library rotation.
Checking each type of component to make sure orientation file makes sense
Verify text on PCB is correct
Look into integrated output RF Filter for future revision or add on SMA Filter board.
http://www.johansontechnology.com/datasheets/low-pass-filters/0915LP15B026.pdf
Ideally this would be viewable in the FaradayRF-Hardware/Mechanical/Drawings
(or similar) folder without the need to pull down zips, enter KiCad, etc. Critical to enthusiasts who want to know how to mount FaradayRF in an enclosure.
I noticed the hole patter of the FaradayRF is not regular (ie 4"x4", etc.). I would be happy to generate a 3D printed adapter (FaradayRF-Hardware/Mechanical/CAD/Mounts
) to transverse the irregular PCB mounts to an "easy to measure out and manufacture at home" variety.
Later revisions of the board may want to consider evolving mounts to a symmetrical pattern. I completely understand the challenge of doing this real-world.
Since it appears we don't actually need to tune this antenna why not simply directly connect copper between pins 4 and 6 of the M104780A2 GPS? Remove inductors for tuning while I'm at it.
Revision B hardware testing has identified several changes that would be ideal to incorporate with a board spin. Most of these are manufacturing related to help ensure a well designed PCB for production.
Removing the soft-start means we can remove the minimum capacitance as more than enough capacitance will be on the bus.
Re-test #14 with code that sends lots of RF data to verify.
Testing performed to validate the design of the 5V USB power supply inrush limiting and USB compliance. Essentially, it's in our best interest to prevent Faraday from causing an inrush event when plugged in and ringing to over-voltage and destroy itself โ
KiCad provides a CSV output for the BOM but it needs to be updated to the latest changes. This should not be affected by panelization.
It is likely that in the future Faraday will split into two main projects:
Texas Instruments provides a basic overview of the radio operations possible with the CC430: http://www.ti.com/lit/an/slaa465c/slaa465c.pdf
The example RF code is located here: http://www.ti.com/lit/zip/slac525
Since all the default port mapping is used for RF GDx pins and it's a secondary function we should implement port mapping. Port mapping is supported on P1, P2, and P3. We should swap 3 of the GPIO pins using port 4 with port 3 pins to allow a GPIO pin to become an RF GD0 pin.
Swap with basic I/O pins used on GPS and other devices:
Recommend swapping:
4.0 <-> 3.2
4.1 <-> 3.3
4.2 <-> 3.4
This Should allow for low risk swapping and peripheral operation while allowing a port mapped GDx signals to the external pins.
No changes needed, all of this is handled in the firmware. Key points:
Synchronous/Asynchronous operation allows for direct access to the CC1101 radio core. This allows for the most flexibility in radio protocols as well as the ability to perform low level protocol processing on a more powerful platform.
Requires the use of internal timers.
Clock timer output to 2.7
Data output 2.6
The CC430 header file snippet above shows Port 3 but Port 2 is the same.
We've already brought up the first of twelve boards on #46 so here are the next 11! Order of building these units will be the same as the first being SMA connector, GPS, and finally Power/MOSFET connectors. None of them will initially get a JTAG connector but they may eventually. Finally I will use prebuilt binaries to update the firmware of the CC430 via USB.
Title says it all. PCB:NG determines plating with presence of copper in hole.
Rev C Gerbers have been checked thoroughly against the Rev B design in #11. Now, I need to make sure changes going to Rev D also make sense.
Create a known-good Rev D BOM
Working through their DFM errors to make an extremely easy to manufacture board
To enable work on PCB:NG placement I need to remove a few parts from the BOM on their website to let me proceed while I wait for their response on how to deal with those part issues.
We actually don't need this. Additionaly, we could hook it back up to an interrupt driven IO pin and flash the main LED or at least indicated in telemetry with or without the Fixed indicator pin.
Create new pick and place files for Rev D1 specialized for PCB:NG's needs.
The attached zip folder contains images showing some poor U1 CC430 solders I discovered today while building up the last 11 units of this test build. Lots of solder beads and some shorts. An example below:
I'll let PCB:NG know so they can adjust any solder or paste manufacturing profiles to prevent this.
The ADC filters are quite a few parts that we should either move to easily solderable components or remove them. This is a tricky one...
Hi, interested in your opinion and I imagine you'll have to make a similar change anyway in the future:
After your Amp Hour appearance, I got impatient for waiting, so I'm building two or three FaradayRF boards based on the REV D board layout. Aside from some careful MLCC substitutions (!@#$%) and the SPI flash that's DNP (and which looks like a standard interface), the significant thing that I couldn't obtain was the GPS M10478-A2 module. An EOL notice from Antenova says to use the M20048, which Digikey didn't have, but I went looking at the M20050-1 and it seems to also be a compatible pinout, except for wanting a 1.8 nH inductor between pin 28 and GND and having a somewhat different antenna. I am actually tempted to just put one in the existing circuit and see how it performs, though I could probably isolate the pad with kapton and bodge in a tiny wire. :)
Thanks!
Referring to PCB:NG's stackup to create 50 Ohm traces for long runs of RF
In the end, flash memory doesn't need to be implemented externally on this version of Faraday. We have a lot to work on that doesn't involve use of the Flash memory IC.
Engineering docs shows Rev C.
This pin is also the external VREF+ input so we dual purpose it.
This ticket holds the inspection, build, and testing of the first PCBA to be built 100% to completion. As arrived from PCB:NG the PCBA's contain all circuitry except through hole components, GPS, and SMA connector. During inspection several key verification need to be addressed:
This board booted good! Have tested basic CC430 operations, no RF. Bryce and I are inspecting for general concerns, no operational issues noted yet but noting anything that looks potentially an issue. We're use to hand soldered components so our experience with automated solder paste fillets are minimal.
Solder SMA connector on, looks good! Verified a quick RF test commanding a REV B1 Faraday remotely, the CC1190 and RF circuitry work! Not sure on performance but seems like a great start.
Booting of the first REV D1 PCBA from PCB:NG. This board has no through hole components, GPS, or SMA antenna connector until it is soldered at a later time. This ticket is to capture the boot process.
Initial Steps Needed
h1. Unboxed PCBA
This PCBA was unboxed and has not had any manually installed parts placed.
h1. USB Connection
h1. Update FTDI IC
h1. USB Connection #2
h1. Firmware Build and Bootloader
I created a branch in firmware from master for the initial boot (https://github.com/FaradayRF/Faraday-Firmware/tree/REV-D1-Initial-Boot).
h2. Create TI HEX Firmware File
Right-click the project and navigate to and enable the TI HEX Utility. The enabled the ti-txt output option
Simply compiling the program will now output a TXT file. I created Faraday_REVD1_Bringup.txt
Copy this file into the bootloader folder and edit the filename in the Auto_Upload.py
to match that of the next .txt file created. Edit the CreateBslScript()
function line in Create_TI-TXT_Parse.py
to match the COM port being used by the device to be programmed.
textfile.writelines(('MODE 6xx UART 9600 COM7 PARITY', '\n'))
Run the Auto_Upload.py file to create a new
FaradayFirmwareUpgradeScript.txt` which contains the bootstrap loader scripting language output. The programming will automatically start!
In the act of programming:
h1. Verify Booting and Basic Operations
h2. See UART Telemetry
Verified proper initial boot of "NOCALL" is being sent over UART! This is the initial factory default settings if no programmed state exists.
h2. Tutorial 1-1 Proxy Basics
I decoded data from the unit!
h2. Tutorial 1-3 Device Configuration
I'm reprogramming the unit from the default NOCALL to KB1LQD-5.
For some reason I keep getting this error, looks like a proxy/device programming script error?
h2. Tutorial 1-4 LED Toggling
Yep, the GREEN LED toggled as intended and UART echo'd back a message!
Title says it all. Analysis indicates that Ground would be connected to the MOSFET drain and VCC would be connected to VCC correctly. This was done by design. At most I expect the body diode of the MOSFET to allow conduction and powering of Faraday. Passing 30mA during GPS + RX should be fine while transmitting could cause damage to the MOSFET. The groundshift could cause unexpected operations but should not cause damage.
Verify power supply layout is optimal
Reorganize the libraries and get the KiCAD 2013 project files to produce a correct ERC and DRC run on a standalone GitHub repository.
The ADC AVCC filter isn't really needed, just keep the decoupling capacitor. We never really use the low frequency watch crystal X1 (32.768 KHz). Should DNP that.
Testing
Simply Looking at the board to see if everything makes sense. Very 10k foot view stuff.
Verify that REV C boards which contain the FTDI traces as tested with flywire correctly load bootloader of TI and program board.
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