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License: GNU General Public License v3.0
Modular cycle-accurate NES emulator implemented from scratch
License: GNU General Public License v3.0
Missing:
9D Absolute,X
99 Absolute,Y
81 Indexed-indirect
91 Indirect-indexed
A lot of the 6502 instructions write even when they have no reason to. We've skipped this in places. We should set up an integration test checking dummy reads/writes and add them as they can cause side-effects.
Having support for mappers 0-5 is probably a good start.
We should set up an integration test running nestest (http://nickmass.com/images/nestest.nes) and verify it against correct output here: http://www.qmtpro.com/~nes/misc/nestest.log
It seems like the negative status flag should always be cleared when doing a LSR operation: https://www.c64-wiki.com/wiki/LSR
LSR affects 3 of the CPU's status flags:
- The negative status flag is always unconditionally cleared.
- The zero flag is cleared unless the operand is zero
- The carry flag is copied from the least significant bit (bit 0) of the operand prior to shifting
We do not clear the negative status flag right now:
case LSR_A:
pipeline_.push([=]() {
set_carry(registers_->a & 1);
registers_->a &= ~1;
registers_->a >>= 1;
set_zero(registers_->a);
});
When doing this we can probably remove the oldest GCC jobs.
Azure devops supports multiple parallel jobs and unlimited build minutes for open source projects. Appveyor's VS2019 job has been broken for weeks and only supports 1 build at a time meaning our Appveyor CI is always what's blocking the longest.
A lot of the functionality between mappers are similar. We should probably have a mapper interface that translates an address on the cpu or ppu bus to a new address, and let the rom memory be owned by a shared rom-object
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