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6.0 6.0 0.0 1.77 MB

SystemVerilog 29.25% Verilog 56.83% Tcl 3.20% C 9.02% C++ 0.36% Coq 1.23% Makefile 0.06% Pascal 0.04%

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fpga-bpf's Issues

No multiply, divide, or mod in ALU

These operations are seldom used, and in fact, complicate the design since they take more than one clock cycle.

However, we should have them.

Very messy packet_length logic

I need to pick a consistent way to manage the packet length logic; right now it's spread between having to do it in the forwarder, CPU, and packetmem.

Very messy parameters in Verilog code

Basically it's very confusing. There's a mix of defines and parameters, and there are no consistent rules.

One particularly confusing aspect is how snoopers and forwarders must increment addresses by 2 instead of 1. I should really just append a zero internally.

Anyway, stuff like that. Code cleanup (and eventual documentation) is always a work in progress,

Code usage

Hi @esophagus-now,
I might want use parts of your code in an educational study that could contribute to commercial product. I tied to reach out to you via [email protected] but without luck.
Is there a possibility for that kind of usage?

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