embecosm / chiphack Goto Github PK

Repository and Wiki for Chip Hack events.

License: Other

Verilog 37.20% Makefile 21.16% Batchfile 15.99% CSS 0.56% Python 20.58% SourcePawn 0.16% C 4.33% Assembly 0.01%

chiphack's Introduction

Chip Hack

This repository (and its companion wiki) contains tutorial code and documentation for the Chip Hack events. Most recently the ChipHack/EDSAC Challenge, held in Hebden Bridge from the 6th to the 8th of September 2017.

Tutorial slides

All the tutorial slide decks can be found in the tutorials directory. Many of these are prepared using Hieroglyph a derivative of . Being based on reStructuredText the content is plain text, making it easy to transfer to other formats.

Each tutorial slide deck has its own directory.

All slide decks are provided under a Creative Commons Attribution-ShareAlike 4.0 license, so you are free to share and modify the slides, so long as you attribute the original authors and give the same rights to others.

Using Hieroglyph

There are guidelines online for setting up hieroglyph. I used version 0.7.1 on top of Sphinx 1.4.1 (there can be an issue with newer versions). With this installed, each set of slides can be built from the individual tutorial directory by running

make slides

The slides will be found as HTML in the build/slides directory. Just open index.html in your browser.

Tutorial code

The tutorial code is in individual subdirectories within the basic_verilog and cheat_sheet directories, with one sub-directory for each exercise. directory.

basic_verilog

The files are mostly empty, for you to complete.

cheat_sheet

Full solutionns corresponding to the basic_verilog files, if you get stuck.

pretty_colours

A full project, with a chip.bin, so that you can test your installation of the tools

Prerequisites

To install everything you need follow the guides on chiphack.org:

To compile and upload programs

Full guidance is provided in the setup presentation (HTML, slides)

chiphack's People

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ramaro cpswan hacklinux soshimozi tienledinh tvtritin changeyourname axiomsofchoice caolan imphil gmarkall jmacarthur defproc githubbabrova mithro nataliastor

chiphack's Issues

Outdated build instructions

Much has happened since these build instructions at https://github.com/embecosm/chiphack/wiki/OpenRISC-tools-install were written. I just got a user who had some trouble with them, and I suggest that much of the contents should be removed, and replaced by links instead

To be more specific,

The build instructions for the OpenRISC bare-metal toolchain is available at http://openrisc.io/newlib/building.html and the instructions for installing FuseSoC can be found at https://github.com/olofk/fusesoc

Unable to run OpenRISC simulation

Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails:
fusesoc sim mor1kx-generic --elf-load hello.elf

I got some warnings like:
WARNING: ::elf-loader:0 : plusargs section is deprecated and will not be parsed by FuseSoC. Please migrate to parameters

And finally I ran into errors:
iverilog -sorpsoc_tb -c mor1kx-generic_0.scr -o mor1kx-generic_0 -DSIM
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_cpu_cappuccino.v:1132: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:87: sorry: constant user functions are not currently supported: calc_rf_addr_width().
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:313: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:331: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.
../src/mor1kx_5.0-r1/rtl/verilog/mor1kx_rf_cappuccino.v:352: error: identifier RF_ADDR_WIDTH is not a parameter in orpsoc_tb.dut.mor1kx0.mor1kx_cpu.cappuccino.mor1kx_cpu.mor1kx_rf_cappuccino.rfspr_gen.
5 error(s) during elaboration.
Makefile:9: recipe for target 'mor1kx-generic_0' failed
make: *** [mor1kx-generic_0] Error 5

I use Ubuntu 16 x64. I did not install Altera Quartus as I plan to use simulation and then go to Xilinx ISE or Vivado.

Please help me to understand the reason.
Many thanks for any help!
With regards,
Maksim

Use SystemVerilog instead of Verilog

The tutorial slides contain (rightfully so) SystemVerilog statements (like always_comb). For those statements to be available to yosys, the easiest way is to rename all *.v files to *.sv and adjust the Makefile accordingly to pick up those files. No other changes to the commands are necessary.

It's probably best to do this after the current tutorial session for the next one to reduce confusion.

Errors during installation of openrisc toolchain-make command in newlib

Makefile:1031: recipe for target 'libc.a' failed
make[5]: *** [libc.a] Error 127
make[5]: Leaving directory '/home/mahadev/or1k/build-newlib/or1k-elf/newlib/libc'
Makefile:683: recipe for target 'all-recursive' failed
make[4]: *** [all-recursive] Error 1
make[4]: Leaving directory '/home/mahadev/or1k/build-newlib/or1k-elf/newlib/libc'
Makefile:641: recipe for target 'all-recursive' failed
make[3]: *** [all-recursive] Error 1
make[3]: Leaving directory '/home/mahadev/or1k/build-newlib/or1k-elf/newlib'
Makefile:452: recipe for target 'all' failed
make[2]: *** [all] Error 2
make[2]: Leaving directory '/home/mahadev/or1k/build-newlib/or1k-elf/newlib'
Makefile:8491: recipe for target 'all-target-newlib' failed
make[1]: *** [all-target-newlib] Error 2
make[1]: Leaving directory '/home/mahadev/or1k/build-newlib'
Makefile:878: recipe for target 'all' failed
make: *** [all] Error 2

Edge detect LED nonsense

Inside basic_verilog/button_edge_detect/edge_detect.v , I try to assign the leds to represent a count to test out the edge detection. It seems to only display the count if one of the leds is being used to represent something else (buttons[0] and a have worked, buttons[1] and b have not).