In file MDR32F9Qx_rst_clk.c in function RST_CLK_PCLKcmd:

assert_param(IS_RST_CLK_PCLK(RST_CLK_PCLK));

If USE_ASSERT_INFO is set to 1 or 2, this expands to the following:

((((((RST_CLK_PCLK) & ((uint32_t)(1 << ((((uint32_t)0x40048000) >> 15) & 0x1F)))) == 0x00) && 
(((RST_CLK_PCLK) & ((uint32_t)(1 << ((((uint32_t)0x400D0000) >> 15) & 0x1F)))) == 0x00) && 
(((RST_CLK_PCLK) & ((uint32_t)(1 << ((((uint32_t)0x400E0000) >> 15) & 0x1F)))) == 0x00) && 
(((RST_CLK_PCLK) & ((uint32_t)(1 << ((((uint32_t)0x400F8000) >> 15) & 0x1F)))) == 0x00))) ? (void)0 : assert_failed(4, 1426));

That last check boils down to (1 << 0x1F) and that triggers a warning because 1 is signed int and that shift touches the sign bit.

This shift comes form macro PCLK_BIT:

#define PCLK_BIT(BASE)              ((uint32_t)(1 << ((((uint32_t)BASE) >> 15) & 0x1F)))

Solution is simple, we need to change 1 to 1u.

Функция должна сбрасывать и устанавливать бит MR но устанавливает еще несколько старших бит,
и сбивает раннее сделаные настройки (ошибка из за неправильгого значения MR_EN_Reset),
предлагается такой вариант:

void MIL_STD_1553_Cmd(MDR_MIL_STD_1553_TypeDef * MIL_STD_1553x, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_MIL_STD_1553_ALL_PERIPH(MIL_STD_1553x));
assert_param(IS_FUNCTIONAL_STATE(NewState));

if(NewState == ENABLE){
	/* Enable the selected MIL_STD_1553 by clearingsetting the MR bit in the CONTROL register */
	MIL_STD_1553x->CONTROL &= ~MR_EN_Set;
}
else{
	/* Disable the selected MIL_STD_1553 by setting the MR bit in the CONTROL register */
	MIL_STD_1553x->CONTROL |= MR_EN_Set; // setting only the MR bit in the CONTROL register
	//MIL_STD_1553x->CONTROL |= ~MR_EN_Reset; // it is wrong, unnecessary high bits are set! (оставил ошибку для сравнения)
}

}

DMA_CtrlDataInitTypeDef DMA_PriCtrlStr;

this structure is created but is not initialized, so call to DMA_Init triggers assert_failed.

Unfortunately I have no idea how to use ETH_DMAPrepare and when to call it. ETH_DMAFrameRx doesn't work in FIFO-mode (i.e. with DMA) if I just call it, so DMA should be prepared.. at some point.. i guess. But when and how exactly? I could not find any example for Ethernet with DMA.

There's a check at the top of file:

#ifdef __cplusplus
extern "C" {
#endif

but there is no corresponding closing part. If compiled with g++ as c++, header spoils everything below to compile with C linkage and compiler gives "error: expected '}' at end of input"

USB (CDC) can't send a packet with size that is a multiple of MAX_PACKET_SIZE.

Similar complaints:

• http://forum.milandr.ru/viewtopic.php?p=18913&hilit=MAX_PACKET_SIZE#p18913
• http://forum.milandr.ru/viewtopic.php?p=11656&hilit=MAX_PACKET_SIZE#p11656

The solution that works is described in the message http://forum.milandr.ru/viewtopic.php?p=12577&hilit=MAX_PACKET_SIZE#p12577

Build log:

emdr1986x-std-per-lib/CMSIS/CM1/CoreSupport/core_cmFunc.h: In function 'uint32_t __get_PSP()':
emdr1986x-std-per-lib/CMSIS/CM1/CoreSupport/core_cmFunc.h:425:21: error: ISO C++1z does not allow 'register' storage class specifier [-Werror=register]
   register uint32_t result;
                     ^~~~~~
emdr1986x-std-per-lib/CMSIS/CM1/CoreSupport/core_cmFunc.h: In function 'uint32_t __get_MSP()':
emdr1986x-std-per-lib/CMSIS/CM1/CoreSupport/core_cmFunc.h:452:21: error: ISO C++1z does not allow 'register' storage class specifier [-Werror=register]
   register uint32_t result;
                     ^~~~~~

The reason, as far as I can tell, is the following. Text in the specification says:

Передатчик начинает работать, прочитав ненулевое поле длины из буфера передатчика.
...
Прочитав слово управления, передатчик перемещает указатель head_X на первое слово пакета данных.

So first data word in the ethernet buffer should be data length (in bytes, as far as I can tell from working code example).

However, ETH_SendFrame does not put frame length as first word in ethernet buffer, it just copies the frame. So first byte of the frame is interpreted as it's length which is incorrect most of the time.

It's more or less straight-forward to fix this for ETH_BUFFER_MODE_LINEAR and ETH_BUFFER_MODE_AUTOMATIC_CHANGE_POINTERS but I'm not sure how to do it for ETH_BUFFER_MODE_FIFO.

Пробежался по библиотеке, но так и не нашёл.

For example, MDR32F9Qx_uart.h uses spaces only, MDR32F9Qx_adciu.h uses tabs only, MDR32F9Qx_adc.h uses both.

It's not big deal but it is unpleasant and inconsistent. I don't even know what is the correct policy for this repo since so many files are different.

I believe we should pick tabs or spaces and make it consistent.

Some macro are wrong in MDR32F9Qx_adc.h. assert_param triggered when the right data input.

Now:

#define IS_ADC1_CH_MASK(MASK) ((((MASK) & ~ADC2_ALL_CH_MSK) == 0) || \
                               ((MASK) == ADC_CH_INT_VREF_MSK)    || \
                               ((MASK) == ADC_CH_TEMP_SENSOR_MSK))

Must be:

#define IS_ADC1_CH_MASK(MASK) (((MASK) & ~ADC1_ALL_CH_MSK) == 0)

Now:

#define IS_ADCx_CONFIG_IT(IT)              (((IT) == ADCx_IT_OUT_OF_RANGE     ) || \
                                            ((IT) == ADCx_IT_END_OF_CONVERSION))

Must be:

#define ADCx_ALL_IT_MSK                    (ADCx_IT_OUT_OF_RANGE | \
                                            ADCx_IT_END_OF_CONVERSION)

#define IS_ADCx_CONFIG_IT(IT)              (((IT) & ~ADCx_ALL_IT_MSK) == 0)

Affected code with EEPROM_*() functions calls.
The code compiled in GCC 5.x.
P.S. Bug is strange and I didn't find why it appears. I'll try to find it.

In structure ETH_InitTypeDef there is a field - Dilimeter. It should be spelled 'Delimiter' (as it was spelled in older versions of SPL where everything was prefixed 'opora', as it is spelled in datasheet and in plain english).

I'm afraid that renaming the filed this will be breaking API change :(

Hello Eldar,

Won't it be the cause of unwanted retransmission of the same message - call the function CAN_ITClearRxTxPendingBit with flag CAN_STATUS_TX_READYas an argument, like into LoopBack_Polling example?

  ...
  // Send message
  CAN_Transmit(MDR_CAN1, tx_buf, &TxMsg);
        // ==> BUF_CON[tx_buf] = PRIOR_0 | EN | TX_REQ;
  i = 0;
  // Wait for the end of transfer
  while(((CAN_GetStatus(MDR_CAN1) & CAN_STATUS_TX_READY) != RESET) && (i != 0xFFF))
  {
    i++;
  }
  // Send message again??? Next call raises TX_REQ
  CAN_ITClearRxTxPendingBit(MDR_CAN1, tx_buf, CAN_STATUS_TX_READY);
        // ==> BUF_CON[tx_buf] |= TX_REQ;
  ...

Thank you for your time,
Vitaly

When I do implementation of assert_failed function and use #define USE_ASSERT_INFO 2, I observed that assert statement occurred in file MDR32F9Qx_usb_device.c line 740

static void USB_EP_SetReady(USB_EP_TypeDef EPx, uint32_t val)
{
  ...
  /* Clear pending bits */
  USB_SetSIS(USB_SIS_Msk);
  ...
}

Function USB_SetSIS uses the IS_USB_SIS_VALUE(...) macro with argument USB_SIS_Msk. Need fix IS_USB_SIS_VALUE macro.

There is an include of the MDR32F9Qx_board.h, which is not present in this repo and, I think, is totally unnecessary:

#if ((__CC_ARM == 0) || (__ARMCC_VERSION < 5000000))
	#include "MDR32F9Qx_board.h"
#endif

I guess it's legacy from the demo project.

In file CMSIS/CM3/DeviceSupport/MDR32F9Qx/startup/system_MDR32F9Qx.c at line 144:

/* Reset the RST clock configuration to the default reset state */
SCB->VTOR = 0x08000000;

Which can be seen as necessary as per datasheet:

Программное обеспечение в privileged режиме может перенести таблицу в другое
место памяти через регистр VTOR. Таблица может располагаться в адресах от 0х00000080 до
0х3fffff80. Подробнее в описании регистра VTOR.

VTOR - значение после сброса 0x00000000

But I can see with my debugger that just after reset startup code from ROM (from address 0) executes and sets VTOR to 0x08000000. So modifying VTOR programmatically is unnecessary. But we should not rely on this behaviour since it's not even mentioned anywhere in datashet (as far as I know).

Setting VTOR programmatically to this value in SystemInit may be undesirable in two cases:

• When using Keil simulator, programmer have to set IROM1 region to 0, because simulator can not start from 0x08000000. If then VTOR is manually set to 0x08000000, no interrupts will work.
• When using custom bootloader which loads user code with some offset from the beginning of the flash memory. Before starting user firmware bootloader will modify VTOR accordingly. If user firmware then sets VTOR back, no interrupts will work correctly.

I propose to do something like this:

#ifndef MDR_DO_NOT_USE_DEFAULT_VTOR
  /* Reset the RST clock configuration to the default reset state */
  SCB->VTOR = 0x08000000;
#endif

so the end-user can disable this feature without modifying this code or manually resetting VTOR again in his main-code.

Доброго времени суток!
В файле структура описана следующим образом:
typedef struct {
__IO uint32_t CPUID; //5
__IO uint32_t ICSR; //6
__IO uint32_t Reserved3; //0
__IO uint32_t AIRCR; //7
__IO uint32_t Reserved4; //0
__IO uint32_t CCR; //8
__IO uint32_t SHP2; //9
__IO uint32_t SHP3; //10
__IO uint32_t SHCSR; //11
} MDR_ECB_TypeDef;

Судя по спецификации между CCR и SHP2 должен быть ещё один зарезервированный регистр, т.к. смещения этих регистров отличаются на 8, а не на 4.

GCC 4.9 was working fine.

$ arm-none-eabi-gcc  -DUSE_MDR1986VE9x -D__START=main -D__STARTUP_CLEAR_BSS
  -mcpu=cortex-m3 -mthumb -O2 -ffunction-sections -fdata-sections
  -Wall -Wextra -Wshadow -Wredundant-decls -pipe 
  -I CMSIS/CM3/CoreSupport -I CMSIS/CM3/DeviceSupport/MDR32F9Qx/inc 
  -I CMSIS/CM3/DeviceSupport/MDR32F9Qx/startup/gcc -I MDR32F9Qx_StdPeriph_Driver/inc    
  -o CMakeFiles/xz.dir/thdparty/MDR32F9Qx_StdPeriph_Driver/src/MDR32F9Qx_eeprom.c.obj  
  -c MDR32F9Qx_StdPeriph_Driver/src/MDR32F9Qx_eeprom.c

When I'll have a time I try to see that issue.

I try to use the NVIC_GetPendingIRQ(SysTick_IRQn), but SysTick_IRQn is not correct argument for this function!

This function and other similar must check the input arguments.

I will make implementation and a pull request.

There is code in the file MDR32F9Qx_config.h:

#if ((__CC_ARM == 0) || (__ARMCC_VERSION < 5000000))
    #include "MDR32F9Qx_board.h"
#endif

I think should remove or somehow modify this code. My reasons below.

• File MDR32F9Qx_board.h didn't exist in repo.
• Macro __CC_ARM never equal 0 in a normal use. Always set to 1 for the ARM compiler or 0 for other. See predefined macros for the ARM compiler and C99 standard specifies.

I'm using IAR and I have an annoying problem with this code. What is your opinion?

EEPROM writing and erasing functions relay on this code for delays:
ProgramDelay(GET_US_LOOPS(5));

GET_US_LOOPS implementation is as follows:

#define GET_US_LOOPS(N) ((uint32_t)((float)(N) * FLASH_PROG_FREQ_MHZ / DELAY_LOOP_CYCLES))

This code triggers a warning on implicit double promotion because FLASH_PROG_FREQ_MHZ is by default defined like this (and therefore is double):
#define FLASH_PROG_FREQ_MHZ (8.0)

But the main problem here is that it is a constant when SYS_CLK can actually change during runtime (by enabling/disabling PLL, for example). So all EEPROM delays will go out of the window.

I suppose FLASH_PROG_FREQ_MHZ should be made dependent on SystemCoreClock variable. And there is no point in making it double or float, since it is used only after convertion to uint32_t);

__RAMFUNC static void ProgramDelay(uint32_t Loops)
{
  volatile uint32_t i = Loops;
  for (; i > 0; i--)
  {
  }
}

I guess it should be something like this (I tried to do a ceiling instead of simple division but I'm 100% sure I did it wrong):
GET_US_LOOPS(N) (N*((SystemCoreClock + 1000000 - 1)/1000000) + DELAY_LOOP_CYCLES - 1)/DELAY_LOOP_CYCLES

In MDR32F9Qx devices in startup code for Keil SystemInit function calling from Reset_Handler before main function. But in startup code for MDR1986VE1T it is not. I suggest to add this feature for MDR1986VE1T startup for Keil.

Also I see, that in scripts for other compilers for MDR1986VE1T this feature already exist.

Reset_Handler in startup_MDR1986VE1T.s for Keil:

Reset_Handler   PROC
                EXPORT  Reset_Handler			[WEAK]
                IMPORT  __main
                LDR     R0,=__main
		BX      R0
                ENDP

Reset_Handler in startup_MDR32F9Qx.s for Keil:

Reset_Handler    PROC
                 EXPORT  Reset_Handler             [WEAK]
        IMPORT  SystemInit
        IMPORT  __main
                 LDR     R0, =SystemInit
                 BLX     R0
                 LDR     R0, =__main
                 BX      R0
                 ENDP

P.S. This is my first try in GitHub, sorry for errors :)

I would like to offer a small improvement for the function
void SystemCoreClockUpdate (void)
from module system_MDR1986VE1T.c

It uses integer division in two places where one can do without it, because both operations manipulates with divisor power of two.

Line 86: cpu_c1_freq /= 2;
Line 114: cpu_c3_freq = cpu_c2_freq / ((uint32_t)2 << tmp);

Since most of the supported microcontrollers does not have division operations, I suggest replacing it with shift operations. If user app does not use integer divisions, it will reduce code size by approximately
300 bytes or more. Also, these operations are performed faster. For the first operations compiler use shift by default, but second is difficult for it.

cpu_c1_freq >>= 1;
cpu_c3_freq = cpu_c2_freq >> (tmp + 1);

If you will be agree with it, I can create pull request.

We can delete the built-in CMSIS (dirs CoreSupport) because it is old and have some issues fixed in the current version of CMSIS 5.
In README I can link to newer CoreSupport.
Are any opinions?

There is a problem with ADC divider.

In Datasheet:

Таблица 294 – Описание бит регистра ADC1_CFG:

Cfg_REG_DIVCLK[3:0]
Выбор коэффициента деления частоты процессора:
0000 – CPU_CLK = HCLK;
0001 – CPU_CLK = HCLK/2;
0010 – CPU_CLK = HCLK/4;
0011 – CPU_CLK = HCLK/8;
…
1011 – CPU_CLK = HCL K/2048
Остальные CPU_CLK = HCLK

In MDR32F9Qx_adc.h:

#define ADC_CLK_div_None   (((uint32_t)0x0) << ADC1_CFG_REG_DIVCLK_Pos) /*!< The input ADC clock devides by 1.     */
#define ADC_CLK_div_2      (((uint32_t)0x1) << ADC1_CFG_REG_DIVCLK_Pos) /*!< The input ADC clock devides by 2.     */
…                        
#define ADC_CLK_div_32768  (((uint32_t)0xF) << ADC1_CFG_REG_DIVCLK_Pos) /*!< The input ADC clock devides by 32768. */

So, if you use divider greater then 2048 ADC will be clocked from HCLK directly.
Checked experimentally.

EEPROM_ReadWord всегда возвращает 0 , даже если данные есть. Настройки задержек верные т.к. с оптимизацией 0 все работает.

See StartMilandr/Pack_VEx#6

Are anyone tested one of these MCU?
Can we change status not tested?

Из-за этого MDR32F9Qx_eth.c даже не компилируется.

Привет!
в макросах SPL MDR32F9Qx по делу и без вставляется приведение к типу (uint32_t). в результате такая константа не может обрабатываться препроцессором в директивах #if
пример:
MDR32F9Qx_can.h:379:
#define CAN_BUFFER_NUMBER ((uint32_t)32)

макро CAN_BUFFER_NUMBER невозможно использовать в:
#if ( CAN_CONNECTIONS_LIMIT > (CAN_BUFFER_NUMBER /2) )

Пример

If this library is not supposed to be used with C++ at all, that's not a problem. Still, here's the problem:

If I create a global object, it's constructor should be called before main. Unfortunately, in startup_MDR32F9Qx.s there is no mention of that. Therefore global constructors are not called at all. That's bad.

If we go and look into startup files for stm32, for example (distributed with cubeMx), we will see something like this:

Reset_Handler:
<...>
  ldr r3, = _ebss
  cmp r2, r3
  bcc FillZerobss

/* Call the clock system intitialization function.*/
    bl  SystemInit
/* Call static constructors */
    bl __libc_init_array <----------------------------- here it is!
/* Call the application's entry point.*/
  bl main
  bx lr

To make this work we should:

• change startup accordingly;

• remove -nostartfiles from linker flags (because __libc_init_array will call __init and it must come from somewhere). This will make total code size bigger; unfortunately, I don't know what can be done about that;

• add -mthumb to linker flags (because by default it will link startfiles compiled into arm code, not thumb).

Проект для QtCreator лежит тут:
https://github.com/WicRus/emdr1986x-std-per-lib-qbs
переработанная библиотек тут:
https://github.com/WicRus/emdr1986x-std-per-lib
В настройке проекта можно выбирать под какой микроконтроллер собирать проект. Есть возможность прошивки и отладки через openocd для поддерживаемых чипов. Компиляцию проекта проверяли на ubuntu и win7.
Если это интересно и есть желание, то можно смержить либу и я ссылку уже перекину на основной проект.

Since startup_MDR32F9Qx.s uses preprocessor, it should be assembled not with as but with gcc, for example, like this:

-x assembler-with-cpp -mcpu=cortex-m3 -mthumb -D__STARTUP_CLEAR_BSS -D__START=main -c

And because readme now recommends adding -nostartfiles (and that's actually is a problem on its own), I had to add -D__START=main; otherwise I got an error undefined reference to _start'`.