eez-open / cf-dic Goto Github PK

Push-Pull MOSFETs can be replaced with cheaper Si type for lower cost.

PCB layout should be optimized for SR (sync rec.) section taking into consideration manufacturers guidelines with special attention to:

• power decoupling
• MOT resistor position and ground connection
• gate drive loops
• source outputs loop
• VS and GND connection
• VD inputs RC filter placement and GND connection

In the BOM document, the package size stated is 1206, but you have ordered 0805 component size and the component size on the PCB is 0805 also. Please check.

For additional safety an on-board fuse (e.g. TR5 size) has to be added.

Add fast OVP circuit by monitoring Vclamp voltage on the primary side to avoid output voltage rise above max. value in case of failure in tracker circuit or if control signal (U_MON) rise above 2.5 V. Reuse a half of LM258 (IC4) currently used for NTC signal buffering and add voltage divider on FB (e.g. 750R + 130K).

External capactior directly connected to ULVO pin affect softstart sequence. Therefore it has to be moved before 1K hysteresis resistor.

CT input filter is too big and introduce unacceptably huge delay. Therefore a control loop was not work properly and for higher Vin (230 Vac) duty was different then for lower Vin and active duty limiter is added to fix that problem.

The package size stated for item no.24 in the BOM document is 0804. Did you mean 0805? Please check.

VD1 i VD2 inputs require filtering to avoid false triggering caused by ringing.

For the dual inductor section, it seems like you would have a shorter routing by rotating both transformers, was there a reason behind the current orientation?

Equally it appears the diode / capacitor for both inductors could be placed on a far shorter loop.

I have to admit at this point Its hard for me to visualize all the current loops for this converter, just working on your footnote to keep the trace lengths even and as close as possible.