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Home Page: https://open-vsx.org/extension/eclipse-cdt/peripheral-inspector
License: MIT License
vscode peripheral inspector
Home Page: https://open-vsx.org/extension/eclipse-cdt/peripheral-inspector
License: MIT License
Type: Bug Report
Describe the bug
Issue
When starting a debug session via Cortex-Debug, in the XPERIPHERAL view, I get the following error message instead of a peripheral list:
To Reproduce
Steps to reproduce the behavior:
"version": "0.2.0",
"configurations": [
{
"name": "JLink - Launch",
"cwd": "${workspaceFolder}",
"executable": "./build/debug/project.out",
"request": "launch",
"type": "cortex-debug",
"interface": "swd",
"svdPath": "${command:device-manager.getDevicePack}",
"device": "${command:device-manager.getDeviceName}",
"runToEntryPoint": "main",
"gdbPath": "arm-none-eabi-gdb",
"servertype": "jlink",
"swoConfig": {
"source": "probe",
"enabled": true,
"swoFrequency": 875000,
"decoders": [
{
"port": 0,
"type": "console",
}
]
}
}
]
}
JLink - Launch
configuration.XPERIPHERAL
view.Expected behavior
A list of my device's peripheral in the view.
Code sample and logs
Cortex-Debug: VSCode debugger extension version 1.12.1 git(652d042). Usage info: https://github.com/Marus/cortex-debug#usage
Reading symbols from arm-none-eabi-objdump --syms -C -h -w <path to my project>/build/debug/project.out
Reading symbols from arm-none-eabi-nm --defined-only -S -l -C -p <path to my project>/build/debug/project.out
Launching GDB: arm-none-eabi-gdb -q --interpreter=mi2
IMPORTANT: Set "showDevDebugOutput": "raw" in "launch.json" to see verbose GDB transactions here. Very helpful to debug issues or report problems
Launching gdb-server: JLinkGDBServer -singlerun -nogui -if swd -port 50000 -swoport 50001 -telnetport 50002 -device EFR32MG24BXXXF1536
Please check TERMINAL tab (gdb-server) for output from JLinkGDBServer
Finished reading symbols from objdump: Time: 46 ms
Finished reading symbols from nm: Time: 59 ms
Output radix now set to decimal 10, hex a, octal 12.
Input radix now set to decimal 10, hex a, octal 12.
<my entry point> () at <path to my source file>
Program stopped, probably due to a reset and/or halt issued by debugger
2
Resetting target
SWO enabled successfully.
Additional context
As you can tell from my settings.json file, I'm using the ARM Device-Manager to resolve which SVD file I need for my device. It correctly identifies it and I can see that it's trying to fetch the correct SVD pack for it, but for some reason, cortex-debug is not able to use it. The SVD part of the configuration was done according to the official extension documentation, by leveraging the ARM Device Manager extension.
EDIT:
Since this is an issue related to the SVD viewer, I opened it under this repo, but let me know if the issue should be moved elsewhere.
Hi,
sorry for the question :) I have not used cortex-debug before and I am not sure what to expect.
I am trying to connect to a qemu like system and see the registers of one of the uarts.
What I did:
created launch.json looks like:
{
"name": "Qemu Attach with GDB",
"type": "cppdbg",
"request": "launch",
"program": "${workspaceFolder}/build/debug/sw/arm64/linux/vmlinux-4.19.4",
"MIMode": "gdb",
"miDebuggerPath": "/usr/bin/gdb-multiarch",
"miDebuggerServerAddress": "localhost:1234",
"cwd": "${workspaceFolder}/build/debug/sw/arm64/linux/linux-4.19.4",
//"useExtendedRemote": true,
"svdPath": "${workspaceFolder}/vscode/svd/arm_uart_pl011.svd",
"logging": { "engineLogging": true, "trace": true, "traceResponse": true },
}
I merged various snippets of svd files together and have now the code below. The cpu part is a lie, the system has a different CPU (Cortex A72) and GIC (GIC400), but I do not now if these parts are relevant for now.
<?xml version="1.0" encoding="UTF-8"?>
<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
<vendor>soundart</vendor>
<name>arm_uart_pl011</name>
<version>1.0</version>
<description>SYS64</description>
<licenseText></licenseText>
<cpu>
<name>CM7</name>
<revision>r0p1</revision>
<endian>little</endian>
<mpuPresent>true</mpuPresent>
<fpuPresent>true</fpuPresent>
<vtorPresent>true</vtorPresent>
<nvicPrioBits>4</nvicPrioBits>
<vendorSystickConfig>false</vendorSystickConfig>
</cpu>
<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
<width>32</width> <!-- bus width is 32 bits -->
<!-- default settings implicitly inherited by subsequent sections -->
<size>32</size> <!-- this is the default size (number of bits) of all peripherals
and register that do not define "size" themselves -->
<access>read-write</access> <!-- default access permission for all subsequent registers -->
<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
<peripherals>
<peripheral>
<name>uart01</name>
<description>ARM Prime Cell PL011</description>
<baseAddress>0x10009000</baseAddress>
<headerStructName>ARM_UART_PL011</headerStructName>
<addressBlock>
<offset>0x0</offset>
<size>0x8</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x8</offset>
<size>0x10</size>
<usage>reserved</usage>
</addressBlock>
<addressBlock>
<offset>0x18</offset>
<size>0x4</size>
<usage>registers</usage>
</addressBlock>
<addressBlock>
<offset>0x1c</offset>
<size>0x4</size>
<usage>reserved</usage>
</addressBlock>
<addressBlock>
<offset>0x20</offset>
<size>0x2c</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>DR</name>
<description>Data Register</description>
<addressOffset>0x0000</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>DATA</name>
<description>DATA</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BE</name>
<description>BE</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OE</name>
<description>OE</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RSR</name>
<description>Receive Status Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BE</name>
<description>BE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OE</name>
<description>OE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ECR</name>
<description>Error Clear Register</description>
<addressOffset>0x0004</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>FE</name>
<description>FE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PE</name>
<description>PE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>BE</name>
<description>BE</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>OE</name>
<description>OE</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>FR</name>
<description>Flag Register</description>
<addressOffset>0x0018</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>CTS</name>
<description>CTS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DSR</name>
<description>DSR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DCD</name>
<description>DCD</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BUSY</name>
<description>BUSY</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFE</name>
<description>RXFE</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFF</name>
<description>TXFF</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXFF</name>
<description>RXFF</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXFE</name>
<description>TXFE</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RI</name>
<description>RI</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IBRD</name>
<description>Integer Baud Rate Register</description>
<addressOffset>0x0024</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>BAUDDIVINT</name>
<description>BAUDDIVINT</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>FBRD</name>
<description>Fractional Baud Rate Register</description>
<addressOffset>0x0028</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>BAUDDIVFRAC</name>
<description>BAUDDIVFRAC</description>
<bitOffset>0</bitOffset>
<bitWidth>6</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>LCR_H</name>
<description>Line Control Register</description>
<addressOffset>0x002C</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>BRK</name>
<description>BRK</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PEN</name>
<description>PEN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>EPS</name>
<description>EPS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>STP2</name>
<description>STP2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FEN</name>
<description>FEN</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>WLEN</name>
<description>WLEN</description>
<bitOffset>5</bitOffset>
<bitWidth>2</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SPS</name>
<description>SPS</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>CR</name>
<description>Control Register</description>
<addressOffset>0x0030</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>UARTEN</name>
<description>UARTEN</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SIREN</name>
<description>SIREN</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>SIRLP</name>
<description>SIRLP</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXE</name>
<description>TXE</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXE</name>
<description>RXE</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DTR</name>
<description>DTR</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RTS</name>
<description>RTS</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RTSEN</name>
<description>RTSEN</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTSEN</name>
<description>CTSEN</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IFLS</name>
<description>Interrupt FIFO Level Select Register</description>
<addressOffset>0x0034</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>TXIFLSEL</name>
<description>TXIFLSEL</description>
<bitOffset>0</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXIFLSEL</name>
<description>RXIFLSEL</description>
<bitOffset>3</bitOffset>
<bitWidth>3</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>IMSC</name>
<description>Interrupt Mask set_Clear Register</description>
<addressOffset>0x0038</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>RIMIM</name>
<description>RIMIM</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>CTSMIM</name>
<description>CTSMIM</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DCDMIM</name>
<description>DCDMIM</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DSRMIM</name>
<description>DSRMIM</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RXIM</name>
<description>RXIM</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXIM</name>
<description>TXIM</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>RTIM</name>
<description>RTIM</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>FEIM</name>
<description>FEIM</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>PEIM</name>
<description>PEIM</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>BEIM</name>
<description>BEIM</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>OEIM</name>
<description>OEIM</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
<register>
<name>RIS</name>
<description>Raw Interrupt Status Register</description>
<addressOffset>0x003C</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>RIRMIS</name>
<description>RIRMIS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CTSRMIS</name>
<description>CTSRMIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DCDRMIS</name>
<description>DCDRMIS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DSRRMIS</name>
<description>DSRRMIS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXRIS</name>
<description>RXRIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXRIS</name>
<description>TXRIS</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RTRIS</name>
<description>RTRIS</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FERIS</name>
<description>FERIS</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PERIS</name>
<description>PERIS</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BERIS</name>
<description>BERIS</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OERIS</name>
<description>OERIS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>MIS</name>
<description>Masked Interrupt Status Register</description>
<addressOffset>0x0040</addressOffset>
<size>32</size>
<access>read-only</access>
<resetValue>0x0</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>RIMMIS</name>
<description>RIMMIS</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>CTSMMIS</name>
<description>CTSMMIS</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DCDMMIS</name>
<description>DCDMMIS</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>DSRMMIS</name>
<description>DSRMMIS</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RXMIS</name>
<description>RXMIS</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>TXMIS</name>
<description>TXMIS</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>RTMIS</name>
<description>RTMIS</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>FEMIS</name>
<description>FEMIS</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>PEMIS</name>
<description>PEMIS</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>BEMIS</name>
<description>BEMIS</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
<field>
<name>OEMIS</name>
<description>OEMIS</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>read-only</access>
</field>
</fields>
</register>
<register>
<name>ICR</name>
<description>Interrupt Clear Register</description>
<addressOffset>0x0044</addressOffset>
<size>32</size>
<access>write-only</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>RIMIC</name>
<description>RIMIC</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>CTSMIC</name>
<description>CTSMIC</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DCDMIC</name>
<description>DCDMIC</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>DSRMIC</name>
<description>DSRMIC</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RXIC</name>
<description>RXIC</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>TXIC</name>
<description>TXIC</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>RTIC</name>
<description>RTIC</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>FEIC</name>
<description>FEIC</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>PEIC</name>
<description>PEIC</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>BEIC</name>
<description>BEIC</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
<field>
<name>OEIC</name>
<description>OEIC</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<access>write-only</access>
</field>
</fields>
</register>
<register>
<name>DMACR</name>
<description>DMA Control Register</description>
<addressOffset>0x0048</addressOffset>
<size>32</size>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<resetMask>0xffffffff</resetMask>
<fields>
<field>
<name>RXDMAE</name>
<description>RXDMAE</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>TXDMAE</name>
<description>TXDMAE</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
<field>
<name>DMAONERR</name>
<description>DMAONERR</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<access>read-write</access>
</field>
</fields>
</register>
</registers>
</peripheral>
</peripherals>
</device>
It validates using svdconv --strict
If I connect to the system I can stop the qemu CPU and see the stack trace. I would expect to see the peripheral view now, but nothing happens. Where do I have to look or launch it?
Type: Feature Request
I am working on the cdt-amalgamator and trying to inspect the peripheral to debug multiple sessions. I triggered the field "definitionPath" in cdt-amalgamator, but it does not work. I investigated the API that "vscode-peripheral-inspector" provided, but it only allows extending the file format.
My question is: Does the "vscode-peripheral-inspector" allow inspecting more than one peripheral to debug session?
Below is the launch.json to debug two RL78 devices, I would like to inspect the peripherals for both in the debug session. I appreciate all the reviews and assistance, thank you.
{
"version": "0.2.0",
"configurations": [
{
"type": "renesas-amalgamator",
"request": "launch",
"name": "Renesas Debug Multiple",
"verbose": false,
"children": [
{
"name": "proc1",
"debugAdapterRuntime": "node",
"arguments": {
"type": "renesas-hardware",
"request": "launch",
"definitionPath": "R5F104BM.sfrx",
"program": "/home/gnurt/e2_studio/workspace/amagamaltor_RLRH/RL78BMG/HardwareDebug/RL78BMG.elf",
"target": {
"deviceFamily": "RL78",
"device": "R5F10BMG",
"debuggerType": "E2"
},
}
},
{
"name": "proc2",
"debugAdapterRuntime": "node",
"arguments": {
"type": "renesas-hardware",
"request": "launch",
"definitionPath": "R5F104LE.sfrx",
"program": "/home/gnurt/e2_studio/workspace/amagamaltor_RLRH/RL78_testamagamator/HardwareDebug/RL78_testamagamator.elf",
"target": {
"deviceFamily": "RL78",
"device": "R5F104LE",
"debuggerType": "E2"
},
}
}
]
}
]
}
Type: Feature Request
Currently, the Peripheral Inspector allows editing of register values by an inline button/icon that appears when hovering with the mouse pointer over a tree element.
It would be beneficial to allow editing of values by double-clicking on an element. Like for example for the VS Code Variables
view. This would make discovery of this feature easier and more intuitive.
With reference to Marus/cortex-debug#736 this extension has now been rebased on the original codebase as of Marus/cortex-debug@056c03f
This means all existing SVD functionality to date has been captured including:
cortex-debug
is installed).onDebug
), they currently only register when cortex-debug
activates.All previous additions (and some new functionality) have been preserved:
readMemory
and writeMemory
DAP commands and activating for any debug session)Support for the generic debug tracker was tried over in #4, but does not work due to the tracker not working in a browser environment. The overhead of a separate package and/or extension outweighs a simple VS Code pub/sub tracker IMO.
Support for the debug-tracker extension (if installed) has been added in #6
This Cortex-Debug Organisation was created as a temporary home for extracting and managing this extension and the extension should ideally be transferred out.
I'm keen to continue to maintain the extension and see two options for a new home:
cortex-debug
Type: Feature Request
The number of peripheral registers and bit fields shown in the peripheral inspector can vary heavily from device to device.
Often their number is quite big and it can be hard to find something specific if you don't know the full register hierarchy in and out.
A search functionality would be extremely useful to quickly find points of interests.
I appreciate that such functionality may not be easy to implement with the current Tree View. But maybe implementation of #21 helps to unblock this/implement it in a user-friendly way.
Type: Feature Request
The Microsoft Tree View is unfortunately limited in functionality for more sophisticated features and styling.
Examples of things that are currently not possible:
We made some good experiences with the PrimeReact GUI library on the Memory Inspector extension. Maybe it is an option to use it's Tree or TreeTable? The latter could have an advantage in showing values in a more aligned way.
Type: Feature Request
Other peripheral register displays allow the use of more sophisticated controls. This can be for entire registers or their bit fields.
For example bit field values that can be enumerated would work well with dropdown boxes. And single bits the represent a boolean value could be shown as checkboxes.
I appreciate that it currently isn't possible to make this real with the current Tree View implementation. But maybe #21 could unblock this.
Type: Feature Request
In its current state, this repo cannot be published to the marketplace because it has the same ID as the original svd-viewer
.
It is possible to move the publisher of this extension to resolve the issue, however existing installs of cortex-debug.svd-viewer
will fail. see: microsoft/vscode-discussions#1 (reply in thread)
Should we try to keep the name or deprecate it in favour of a new name, e.g.:
A declarative, efficient, and flexible JavaScript library for building user interfaces.
๐ Vue.js is a progressive, incrementally-adoptable JavaScript framework for building UI on the web.
TypeScript is a superset of JavaScript that compiles to clean JavaScript output.
An Open Source Machine Learning Framework for Everyone
The Web framework for perfectionists with deadlines.
A PHP framework for web artisans
Bring data to life with SVG, Canvas and HTML. ๐๐๐
JavaScript (JS) is a lightweight interpreted programming language with first-class functions.
Some thing interesting about web. New door for the world.
A server is a program made to process requests and deliver data to clients.
Machine learning is a way of modeling and interpreting data that allows a piece of software to respond intelligently.
Some thing interesting about visualization, use data art
Some thing interesting about game, make everyone happy.
We are working to build community through open source technology. NB: members must have two-factor auth.
Open source projects and samples from Microsoft.
Google โค๏ธ Open Source for everyone.
Alibaba Open Source for everyone
Data-Driven Documents codes.
China tencent open source team.