Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. Intended for creators Yiming Gan and Dylan Vanmali.
feel sorry to issue about your personal courses project after years, I am a students from china and this repo helps me a lot, but maybe there is a lack of pipede.v that register module between decode and execute stage. Am I right ? I am still studying about my architecture , Maybe I can give a PR until I fully understand branchpredict and hazardcontroll in this repo.
btw, this is my first issue on github, if i do sth wrong please forgive and tell me, thanks.