Handy generic VHDL modules that can be used as part of a VHDL project. Every VHDL module has been simulated and should work as intended. Test bench files of the simulation are included in the module's appropriate directory as well. An ISE project file is also published with all the VHDL modules set up, and so they can be tested before the real use. The modules are not intended to be top-level entities of projects.

• Clock Divider
• First In, First Out
• Last In, First Out
• Memory Copier
• Parallel In, Serial Out
• Pulse-Width Modulation
• Random-Access Memory
• Read-Only Memory
• Serial In, Parallel Out
• Seven-Segment Display Driver
• Static Clock Divider

The modules are documented inside their VHDL source files using comment headers and inline comments.

• support.md – questions, answers, help
• contributing.md – how to get involve
• license – author and license