The clock should be removed from this interface. It will then be up to IP cores to declare the TMDS clock as a differential clock interface with the ASSOCIATED_BUSIF properly set. This should help clock constraints propagate through the tools more smoothly.

will you be adding PmodAMP3 to the pmod section any time soon?

[DRC REQP-161] connects_CLKINSEL_VCC_connects_CLKIN1_ACTIVE: top_i/pixel/rgb2dvi_0/U0/ClockGenInternal.ClockGenX/GenPLL.DVI_ClkGenerator: The PLLE2_ADV with CLKINSEL tied high requires the CLKIN1 pin to be active.

This is the error I get when I attempt to generate a bitstream with a rgb2dvi component in my design. (https://forum.digilentinc.com/topic/17999-dvi2rgb-issue-plle_adv/) Any suggestions?

ERROR: [Place 30-487] The packing of instances into a set of slices defined by an internal area constraint could not be obeyed. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced. ... Names of first 20 cells: dbg_hub/inst/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_en_1_reg[0] ...

The error message is telling us that there is too much logic driven by the MIPI D-PHY RxByteClkHS and it cannot be placed. Since this clock is driven by a BUFR, any logic driven by it needs to be placed in a single clock region and this seems to be an impossible task for the placer. When the Debug Module option is enabled in either the D-PHY or CSI-2 IPs the quantity of logic driven by this clock increases dramatically.
However, some of that can be clocked by a different clock, enabling the placer to move that logic to a different region and relieve congestion there. Choose a different high-frequency clock and add the following to your top-level xdc:

set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets system_i/mm_clk_150]

Replace system_i/mm_clk_150 with an actual clock from your design.

Hello,

I've been using the PModSD IP and code with a lot of success. Thank you for developing this. What I would like to know is, how can I speed up the data transfer?

I've tested the IP core with a microblaze on an ARTY board and on a ZYBO with a zync. The data rates top off at about 100kB/sec. It appears the bottleneck is at the SPI/SDCS interface? I'm not sure.

If someone can point me to where I can get started update dating the IP or the software to speed up the data throughput of PModSD, I will be a very happy camper.

Thanks!

Hello,
I am trying to run the PmodGPS example code, but after copying the code into my main.c file, I see multiple definitions missing:

1 - 'INTC' does not name a type ---- line 69
2 - 'XPAR_INTC_0_DEVICE_ID' was not declared in this scope ---- line 86
3 - 'XPAR_INTC_0_PMODGPS_0_VEC_ID' was not declared in this scope ---- line 87

Based on atangzwj comments, this example has beed tested on Vivado 2017.4 recently. I made sure that the related header file ("xintc.h") exists in the SDK directory, but whatever the problem is, it seems these type and character are not defined properly. Is there anyone who can help me with this?
Best,
Mahdi

I've been attempting to use Pmods with my Arty-S70-50 board in Vivado and the only option I am given is the PmodBLE. I've noticed that when I select the generic Arty board that I am able to load the entire set of Pmods. I'm guessing this is related to this issue in the Xilinx forum. Is there no support for Pmods other than the PmodBLE with the Arty-S7-50 or is this a Vivido issue?

Hello,

I am trying to simply read the GPS data with Arty board and write it to SD card. For this purpose, I tried to combine the example codes of two modules provided here, but apparently PmodSD code is written in C++, while PmodGPS code is written in C, which makes it a bit difficult to combine. I am planning to write my code in C++, so the PmodSD code is working fine for me, but when I am trying to initialize or call GPS functions, I receive this error:

"undefined reference to `GPS_begin(PmodGPS*, unsigned long, unsigned long, unsigned long)' ".

I guess this means GPS header files are not included, but that is not the case here, because I have made sure to include all the necessary header files correctly. Does anybody know what could be the problem? I also get the same kind of error, when I use a PmodNAV which is also written in C.

Hello, I use Vivado 18.1 and the vivado-library.
If I create a block design for the zybo z20 with several pmods.
Problem: in the SDK the pmods drivers from this library do not appear in the bsp.
The hdf shows all Pmods but the drivers are wrong.

Thanks in advance
Thomas

Description
The Dynamic Reconfiguration Port allows users to modify the behavior of the MMCM at runtime. the dynclk is used to modify the clock frequency at runtime but it looks like the part of the module used to configure the feedback does not have the correct address.

File Location
mmcme2_drp

Line 123:

      // Store CLKFBOUT additional frac values
      assign rom[4] = {7'h13, 16'hC3FF, 2'b00 , S1_CLKFBOUT[35:32], 10'h000};

This line configures the clock feedback value.

I believe the address '7'h13' should be '7'h14'

Xilinx Application Note
On page 10 of XAPP888

Address 0x13: CLKOUT6 Register 2 (Not available for PLLE2 or PLLE3)
Address 0x14: CLKFBOUT Register 1

Note
I thought that there might have been a change between the 2012 and the 2016 version of the application note but there is not. 0x14 has been the CLKFBOUT register.

The PmodBT2 SPI header is not standard, so the hardware pins need to be swapped in the IP core. SPI is only used to update the firmware of the BT2, so the BT2 still works.

IP names are inconsistent with use of capitalization, underscores, and version numbers. Guidelines need to be communicated and followed that define the naming conventions. Existing IP's should then be changed to follow the guidelines.

Changing the names should not cause mass issues, because the use of submodules should prevent our projects from breaking until they are deliberately updated. It will likely break the auto update feature of Vivado though, so they may need to be manually removed and replaced in the projects during the next round of maintenance (unless someone can find out how to make Vivado recognize an IP with a different name as the more recent version of the previously used IP).

1.) I have tried adding the repos to Vivado 2018.2 but they do not seem to be recognized as IP.
2.) All the IP from this repo when referenced in the Zybo-hdmi-in and Zybo-hdmi-out projects are locked.

I cannot figure out how to upgrade/regenerate them since they do not come with their own Vivado projects.

A BUFMR was added on the output of the MMCM in order to get this core to work with Nexys Video. Doing this allows the MMCM that is instantiated to be in the bank above or below the bank attached to the HDMI port. This was necessary on the Nexys Video because both the HDMI input and output are on the same bank, and HDMI input requires an MMCM too. The problem with this work around is that it causes a timing error due to pulse width on the BUFMR for typical video frequencies, despite still working (at least in the case of the Nexys Video).

Adding the BUFMR needs to be brought up to the GUI as a parameter that can be disabled, since it is not necessary in most cases.

Conversion Errors

The conversion between meters and feet have been inverted in the PmodNav example code.

Feet to Meters

Should be corrected to the following:

float NavDemo_ConvFeetToMeters(float feet) {  
	return feet * 0.3048;  
}

Meters to Feet

Should be corrected to the following:

float NavDemo_ConvMetersToFeet(float meters) {
	return meters * 3.28084;
}

Premature Rounding of Pressure Reading

The calculation of hPa uses integer division, thus, the decimal part of the hPa is lost:

The decimal part can be retained by casting dataRawFull to a float:

InstancePtr->hPa = ((float)dataRawFull / 4096);

Where are the Ip cores, which are needed for this proj: https://reference.digilentinc.com/reference/add-ons/pcam-5c/reference-manual#software_support

When you don't select the new option to include the debug module, there are several critical warnings that get generated during OoC synthesis due to the XDC not finding the ILA signals. I think the solution will be to figure out how to conditionally include the XDC constraints related to the debug core based on the users choice for the parameter. Here are the generated critical warnings:

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_refclk'. The XDC file /home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_refclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

CRITICAL WARNING: [Designutils 20-1280] Could not find module 'ila_pixclk'. The XDC file /home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_pixclk/ila_v6_2/constraints/ila.xdc will not be read for any cell of this module.

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:1]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_15/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:2]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_regs/reg_1a/I_EN_CTL_EQ1.U_CTL/xsdb_reg_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:3]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:4]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_in_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:5]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.halt_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:6]

CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_cells -hierarchical -filter { NAME =~  "*ila_core_inst/u_ila_reset_ctrl/asyncrounous_transfer.arm_out_transfer_inst/dout_reg*" && IS_SEQUENTIAL }]'. [/home/digilent/work/git/Arty-Z7-20-base-linux/src/bd/Arty_Z7_20/ip/Arty_Z7_20_dvi2rgb_0_0/src/ila_timing_workaround.xdc:7]

Serial FIFO buffer has a chance to miss data if not polled constantly. Needs a UART interrupt or a larger RX FIFO buffer.

WARNING: [IP_Flow 19-395] Problem reading Component: see 'xilinx:coreExtensions' near line 0 in d:/vivado-library/ip/Pmods/PmodSD_v1_0/component.xml: Bad end of element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file d:/vivado-library/ip/Pmods/PmodSD_v1_0/component.xml. This IP will not be included in the IP Catalog.
WARNING: [IP_Flow 19-395] Problem reading Component: see 'xilinx:coreExtensions' near line 0 in d:/vivado-library/ip/Pmods/PmodWIFI_v1_0/component.xml: Bad end of element
CRITICAL WARNING: [IP_Flow 19-1977] Unable to read IP file d:/vivado-library/ip/Pmods/PmodWIFI_v1_0/component.xml. This IP will not be included in the IP Catalog.

"SyncAsync.vhd" should be complied before "SyncBase.vhd“ do. If not ，It can‘t run simulation，In modelsim or Isim .
:-)
--@--Young--@--

When trying to compile a project with PMOD OLED using Vitis, the platform does not compile on Windows 10 because of

mb-ar: *.o Invalid Argument

According to the following forum post, this is due to changes in the MINGW toolchain.

Forum Post

Also according to that forum post, updating the Makefile solves the problem:

COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a

RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}

INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
ASSEMBLY_OBJECTS  = $(addsuffix .o, $(basename $(wildcard *.S)))
INCLUDEFILES=*.h

libs:
	echo "Compiling PmodOLED..."
	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} ${ASSEMBLY_OBJECTS}
	make clean

include:
	${CP} $(INCLUDEFILES) $(INCLUDEDIR)

clean:
	rm -rf ${OBJECTS} 
	rm -rf ${ASSEMBLY_OBJECTS}

Tested and works.

Hello,
I realized that some Pmods libraries were not compiling in Linux out of the box (latest vivado-library 2016, and Vivado 2017.4). Specifically the Wifi and SD Pmods. I'm learning Vivado so it was a challenge figuring out why the BSP wasn't compiling. After spending some time I realized the Makefile's syntax was not Linux compatible. Also, the Wifi Pmod had some Header files with capitalization issues. I was able to fix the BSP files to compile but then realized I wasn't able to run the programs on the hardware since they were not the same as the files in the wrapper_hw_platform. After I updated the vivado-library source files for those Pmods in question, updated the IP's, recreated the bitstream I was able to run the examples. I wanted to leave a not in case someone else runs into this issue and also perhaps the files can be updated on the next release.
Thanks,
Leo.

It has been reported that commit 3857c15 may have increased some delays that did not need to be increased. Evaluate the usleep commands that were changed outside of the device initialization to be sure that they actually need to be milliseconds long. The values should be compared to other oledRGB code for MPIDE/Arduino to verify.

Implementation failure in vivado when InputSERDES.vhd is included in design

The PmodOLEDrgb fails to build when Generate Out of Context IP is started. I get these fatal errors:

I have tried this in Vivado 2018.3 under Windows and Vivado 2018.2 under Linux and got the same result. I have shortened the path as much as is reasonable (given the Windows path size limit) and I doubt that's the issue since I was able to build an identical design with the previous release and it synthesized and implemented correctly.

The board type is Nexys4 DDR but I am not using the board package. Instead I added the Digilient IP repository to my project and added the PmodOLEDrgb using the Add IP command and specified the FPGA type in the project settings window.

Thanks
Roy

Hello guys,
I managed to run the RTCC example code on my Arty board, but I am receiving a pre-defined date and time over my terminal, which kind of seems useless, since I need the RTTC pmod to find the actual time for me and print that out. Isn't that what RTCC is used for? or maybe it is just the example code that does not synchronize the time? Is there any other example code I can use to get the actual time?
Thanks
Mahdi

When using an externally generated serial clock the -source constraint added by the core seems to assume that serial clock is directly generated by the pixel clock, which doesn't make much sense (if anything it would be vice versa via a BUFR, but that is not always the case either). This causes several critical warnings and seems to confuse the clocking analysis.

Unless this constraint is serving some purpose, I think it should be removed. The clock generation should be handled by the upstream core that actually generates the clocks.

Per the "Drawing Rectangle" section of page 32 of the SSD1331 datasheet, bits corresponding to color A and color C include 1 bit of padding. This means fillColor should be padded in four places inside the OLEDrgb_DrawRectangle function as written below. I have tested and verified these revisions.

   cmds[7] = OLEDrgb_ExtractRFromRGB(lineColor) << 1;   // R
   cmds[8] = OLEDrgb_ExtractGFromRGB(lineColor);   // G
   cmds[9] = OLEDrgb_ExtractBFromRGB(lineColor) << 1;   // B

   cmds[10] = OLEDrgb_ExtractRFromRGB(fillColor) << 1;  // R
   cmds[11] = OLEDrgb_ExtractGFromRGB(fillColor);  // G
   cmds[12] = OLEDrgb_ExtractBFromRGB(fillColor) << 1;  // B

Hi,

https://github.com/Digilent/vivado-library/blob/master/ip/Pmods/PmodRTCC_v1_0/drivers/PmodRTCC_v1_0/src/PmodRTCC.c

line 767: u8 rgbSec[0];

should be: u8 rgbSec[2];

Greetings from Austria

Hello,

I want to use Digilent PMODSF3 with self-designed risc-v core & SoC, therefore I need a version of PMODSF3 driver & tests that can be runned on gnu toolchain but not on Xilinx SDK.
Could you please provide me some instruction on how to port the api?

Thank you very much!
Yun-Chen Lo, Tsing Hua University, Taiwan

How to change the EDID file to make the PC recognize 720p @ 25Hz instead of 60hz?

Hello,
I have been trying to use PmodSD library example to create a simple text file on SD card and write to it, but after successfully generating a simple bitstream in Vivado 2017.4, and launching SDK software, I face multiple difficulties in building the code. Is there any Linux tutorial on how to do this in order and correctly? I have created the application project, and imported the source files from source folder. What are the next steps to do before programming FPGA and running the code? Any help or hint is highly appreciated.
Mahdi

There is no IP catalog entry for PmodVGA. Would it be possible to get his added?

Hello, I installed Vivado 2020.2 on a new machine, and tried to get the PMOD AD5 working by following these instructions (I had it working before on a 2018.3 machine without issues). Bitstream failed with the following errors:

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: jc_pin9_io, jc_pin8_io, jc_pin7_io, and jc_pin10_io.

[DRC UCIO-1] Unconstrained Logical Port: 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: jc_pin9_io, jc_pin8_io, jc_pin7_io, and jc_pin10_io.

I'm using a Zybo Z7-20.

How do I fix this?

Can you please add support for this board DSDB.

AXI Timer IP clock frequency, macro TIMER_FREQ_HZ (drivers/examples/main.c) assumed to be 100MHz for example code, this should be brought up from hardware through xparameters. Possibly create an ext_timer_clk for the AXI_TIMER to be driven at 50MHz.

Hi all,

I have a Pmod DA4 chip and I'm using with the Pynq-Z1 board as a two channel custom function generator. As of now I'm using the base overlay provided by the Pynq project to access the PmodB port through Python.

I want to make my overlay more custom and I was wondering if using the Pmod DA1 provided IP could still work with the Pmod DA4 chip.
Also, will there ever be a Pmod DA4 IP released in this vivado library?

Thanks,
Luke

What is the purpose of the GPIO_interrupt and SPI_interrupt pin of the PmodCAN block? How can I use these?

Sorry to bother you again.I have already constrained the clock <create_clock -period 13.468 [get_ports TMDS_Clk_p]>(720P 74.25Mhz),but there was an error in the implementation:

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_dvi2rgb_0/U0/TMDS_ClockingX/ CLK_IN_hdmi_clk] >

So I use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file,the error disappeared, but the ILA was not found,I can't debug.By the way,the type of FPGA I use is xc7z020clg400

The drivers and hardware do not provide support to control the second digital-analog converter (input D1).
Likely requires a redo of the block design for the IP.

I have added the downloaded the vivado-library directory went to settings and added the path to vivado-library. My problem is under the Board tab there is not connections including the ja, jb, etc.. nor anything for HDMI.

Documentation needs to be updated to reflect changes to the EDID and customization parameters. It should also be reved to v1.6 when this is corrected.

The source folders for the sub-IP used in the usb2device core use over 100 MB and account for over 2/3 of entire vivado-library repo's size. This is pretty serious, because it is contributing significant bloat to all the projects that use this repo as a submodule.

Typically only the .xci and .xml need to be version controlled, though their may be some exceptions such as .coe's for memory IP.

Manual upgrade to 2019.1 required, may be difficult to disable core containers

I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller).
Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else.
I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there.

For making the connections, I've followed the schematic in the reference manual

The IP instantiation is the simplest one: without dinamic calibration or SPI commands.

The "trash data" that I'm getting comes from (see below) adc_data_out_ch1 (I'm not using CH2), and by "trash data" I mean nonsense values, for example, very unstable output values when I have a constant analog input (even with 0V).

I'm reading convertions at ADC's system clock posedge.

I'm posting pieces of my top level design and so the constraint I've used:

/* TOP */
module top
(
    input   i_reset,            /* onboard button   */
    input   i_clock,            /* 125 MHz onboard  */
    
    output  o_tx,               /* uart output      */
    
    output  syzygy_d_n_0,       /* sc1_ac_l         */
    output  syzygy_d_p_0,       /* sc1_ac_h         */
    output  syzygy_d_n_1,       /* sc2_ac_l         */
    output  syzygy_d_p_1,       /* sc2_ac_h         */
    output  syzygy_d_n_2,       /* sclk_sc          */
    inout   syzygy_d_p_2,       /* sdio_sc          */
    output  syzygy_d_n_3,       /* sc2_gain_l       */
    output  syzygy_d_p_3,       /* sc2_gain_h       */
    input   syzygy_d_n_4,       /* data 2           */
    input   syzygy_d_p_4,       /* data 9           */
    output  syzygy_d_n_5,       /* sc1_gain_l       */
    output  syzygy_d_p_5,       /* sc1_gain_h       */
    input   syzygy_d_n_6,       /* data 4           */
    input   syzygy_d_p_6,       /* data 3           */
    output  syzygy_d_n_7,       /* com_sc_l         */
    output  syzygy_d_p_7,       /* com_sc_h         */
    input   syzygy_s_16,        /* data 5           */
    input   syzygy_s_17,        /* data 8           */
    input   syzygy_s_18,        /* data 6           */
    input   syzygy_s_19,        /* data 10          */
    input   syzygy_s_20,        /* data 7           */
    input   syzygy_s_21,        /* data 11          */
    input   syzygy_s_22,        /* data 1           */
    input   syzygy_s_23,        /* data 12          */
    input   syzygy_s_24,        /* data 0           */
    input   syzygy_s_25,        /* data 13          */
    output  syzygy_s_26,        /* cs_sc1n          */
    output  syzygy_s_27,        /* sync_adc         */
    output  syzygy_c2p_clk_n,   /* adc clock in n   */
    output  syzygy_c2p_clk_p,   /* adc clock in p   */
    input   syzygy_p2c_clk_p,   /* clkout adc       */
    output  syzygy_p2c_clk_n    /* GND              */
);      
    
    /* System */
    wire            clock;
    wire            locked;
        
    /* ADC */
    localparam  ADC_DATA_OUT_SIZE   =   16;
    localparam  ADC_DATA_IN_SIZE    =   14;
    wire                                    adc_init_done;
    wire                                    adc_clock;
    wire    [ ADC_DATA_OUT_SIZE - 1 : 0 ]   adc_data_out_ch1;
    wire    [ ADC_DATA_OUT_SIZE - 1 : 0 ]   adc_data_out_ch2;
    wire    [ ADC_DATA_IN_SIZE  - 1 : 0 ]   adc_data_in;
    wire                                    adc_test_mode;
    wire                                    adc_fifo_empty_ch1;
    wire                                    adc_fifo_empty_ch2;
    integer                                 adc_data_count;
    
    assign  syzygy_p2c_clk_n    =   1'b0;
    assign  adc_test_mode       =   1'b0;
    assign  adc_data_in[ 0  ]   =   syzygy_s_24;
    assign  adc_data_in[ 1  ]   =   syzygy_s_22;
    assign  adc_data_in[ 2  ]   =   syzygy_d_n_4;
    assign  adc_data_in[ 3  ]   =   syzygy_d_p_6;
    assign  adc_data_in[ 4  ]   =   syzygy_d_n_6;
    assign  adc_data_in[ 5  ]   =   syzygy_s_16;
    assign  adc_data_in[ 6  ]   =   syzygy_s_18;
    assign  adc_data_in[ 7  ]   =   syzygy_s_20;
    assign  adc_data_in[ 8  ]   =   syzygy_s_17;
    assign  adc_data_in[ 9  ]   =   syzygy_d_p_4;
    assign  adc_data_in[ 10 ]   =   syzygy_s_19;
    assign  adc_data_in[ 11 ]   =   syzygy_s_21;
    assign  adc_data_in[ 12 ]   =   syzygy_s_23;
    assign  adc_data_in[ 13 ]   =   syzygy_s_25;
    
    /* ###################################### */
    clk_wiz_0
    u_clk_wiz_0
    (
        .clk_in1                (i_clock),
        .reset                  (i_reset),
        .clk_out1               (clock),            /* sys clock: 100MHz    */
        .clk_out2               (adc_clock),        /* adc clock: 400MHz    */
        .locked                 (locked)
    );
    /* ###################################### */
    ZmodADC1410_Controller_0
    u_ZmodADC1410_Controller_0
    (
        .SysClk             (clock),                //  IN STD_LOGIC;
        .ADC_InClk          (adc_clock),            //  IN STD_LOGIC;
        .sRst_n             (locked),               //  IN STD_LOGIC;
        .sInitDone_n        (adc_init_done),        //  OUT STD_LOGIC;
        .FIFO_EMPTY_CHA     (adc_fifo_empty_ch1),   //  OUT STD_LOGIC;
        .FIFO_EMPTY_CHB     (adc_fifo_empty_ch2),   //  OUT STD_LOGIC;
        .sCh1Out            (adc_data_out_ch1),     //  OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        .sCh2Out            (adc_data_out_ch2),     //  OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
        .sTestMode          (adc_test_mode),        //  IN STD_LOGIC;
        .adcClkIn_p         (syzygy_c2p_clk_p),     //  OUT STD_LOGIC;
        .adcClkIn_n         (syzygy_c2p_clk_n),     //  OUT STD_LOGIC;
        .adcSync            (syzygy_s_27),          //  OUT STD_LOGIC;
        .DcoClk             (syzygy_p2c_clk_p),     //  IN STD_LOGIC;
        .dADC_Data          (adc_data_in),          //  IN STD_LOGIC_VECTOR(13 DOWNTO 0);
        .sADC_SDIO          (syzygy_d_p_2),         //  INOUT STD_LOGIC;
        .sADC_CS            (syzygy_s_26),          //  OUT STD_LOGIC;
        .sADC_Sclk          (syzygy_d_n_2),         //  OUT STD_LOGIC;
        .sCh1CouplingH      (syzygy_d_p_0),         //  OUT STD_LOGIC;
        .sCh1CouplingL      (syzygy_d_n_0),         //  OUT STD_LOGIC;
        .sCh2CouplingH      (syzygy_d_p_1),         //  OUT STD_LOGIC;
        .sCh2CouplingL      (syzygy_d_n_1),         //  OUT STD_LOGIC;
        .sCh1GainH          (syzygy_d_p_5),         //  OUT STD_LOGIC;
        .sCh1GainL          (syzygy_d_n_5),         //  OUT STD_LOGIC;
        .sCh2GainH          (syzygy_d_p_3),         //  OUT STD_LOGIC;
        .sCh2GainL          (syzygy_d_n_3),         //  OUT STD_LOGIC;
        .sRelayComH         (syzygy_d_p_7),         //  OUT STD_LOGIC;
        .sRelayComL         (syzygy_d_n_7)          //  OUT STD_LOGIC
    );
    /* ###################################### */

endmodule

/* CONSTRAINT */
## 125MHz Clock from Ethernet PHY
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { i_clock }]; #IO_L12P_T1_MRCC Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { i_clock }];

## Buttons
set_property -dict { PACKAGE_PIN C18   IOSTANDARD LVCMOS33 } [get_ports { i_reset }]; #IO_L11N_T1_SRCC Sch=btn[1]

## Syzygy Port A
set_property -dict { PACKAGE_PIN N20  IOSTANDARD DIFF_SSTL18_I } [get_ports { syzygy_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
set_property -dict { PACKAGE_PIN N19  IOSTANDARD DIFF_SSTL18_I } [get_ports { syzygy_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
set_property -dict { PACKAGE_PIN T17  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_0 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
set_property -dict { PACKAGE_PIN T16  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_0 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
set_property -dict { PACKAGE_PIN T19  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_1 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
set_property -dict { PACKAGE_PIN R19  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_1 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
set_property -dict { PACKAGE_PIN T18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_2 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
set_property -dict { PACKAGE_PIN R18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_2 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
set_property -dict { PACKAGE_PIN P18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_3 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
set_property -dict { PACKAGE_PIN P17  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_3 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
set_property -dict { PACKAGE_PIN R16  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_4 }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
set_property -dict { PACKAGE_PIN P16  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_4 }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
set_property -dict { PACKAGE_PIN P15  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_5 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
set_property -dict { PACKAGE_PIN N15  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_5 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
set_property -dict { PACKAGE_PIN K18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_6 }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
set_property -dict { PACKAGE_PIN J18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_6 }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
set_property -dict { PACKAGE_PIN K21  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_7 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
set_property -dict { PACKAGE_PIN J20  IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_7 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
set_property -dict { PACKAGE_PIN M20  IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
set_property -dict { PACKAGE_PIN M19  IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
set_property -dict { PACKAGE_PIN L19  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_16 }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
set_property -dict { PACKAGE_PIN K20  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_17 }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
set_property -dict { PACKAGE_PIN L18  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_18 }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
set_property -dict { PACKAGE_PIN K19  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_19 }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
set_property -dict { PACKAGE_PIN L22  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_20 }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
set_property -dict { PACKAGE_PIN J22  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_21 }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
set_property -dict { PACKAGE_PIN L21  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_22 }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
set_property -dict { PACKAGE_PIN J21  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_23 }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
set_property -dict { PACKAGE_PIN N22  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_24 }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
set_property -dict { PACKAGE_PIN P22  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_25 }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
set_property -dict { PACKAGE_PIN M21  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_26 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
set_property -dict { PACKAGE_PIN M22  IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_27 }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]

Any help would be apreciated.

https://forum.digilentinc.com/topic/18605-pmod-oledrgb-really-oledgrb/