Description

According to the comment in source file, the latest update of this project is in 2014. However, 5 years later the ARTYA7-100T REV.E has come to market. The error is the serial output terminal does not receive any printing from the board, rather than non-ASCII string. I believe the reason why UART control is failed in the new board, is that the internal clock is 450MHz instead of 100MHz. The VHDL code about clock or timer constant seems to be the problem.

Source code reference

in GPIO_demo.vhd:

constant TMR_CNTR_MAX : std_logic_vector(26 downto 0) := "101111101011110000100000000"; --100,000,000 = clk cycles per second
constant TMR_VAL_MAX : std_logic_vector(3 downto 0) := "1001"; --9

constant RESET_CNTR_MAX : std_logic_vector(17 downto 0) := "110000110101000000";-- 100,000,000 * 0.002 = 200,000 = clk cycles per 2 ms

in UART_TX_CNRL.vhd:

constant BIT_TMR_MAX : std_logic_vector(13 downto 0) := "10100010110000"; --10416 = (round(100MHz / 9600)) - 1
constant BIT_INDEX_MAX : natural := 10;

Comment

The source code comes from Nexys4DDR GPIO/UART Demonstration Project, and cut a few components to adapt this board, such as 7-segment display. I don't know how the constants of timer are simulated, though it is defined clearly by the name and line comment. Those constants show once in all project files, and the constraint file does not include these constant.