This project forked from adityatripathiiit/python-based-automated-verilog-code-generator-for-arithmetic-unit
This Project has been done under prof. Joycee Makie @ IIT Gandhinagar. The project contains tools to generate codes and implementation of arithmetic operations on a FPGA.
License: Apache License 2.0
My name is Devvrat Joshi. I am a thrid year undergraduate in Computer Science and Engineering at IIT Gandhinagar. I am interested in Software and Web-Application development. I love competitive coding. I read a lot of research in the field of Machine Learning and Data Science.
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