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Individual Contributions to my team's CPEN 391 final project. I developed the video frame capture system for the D8M, created Avalon slaves for hardware-software interfacing and the DCT hardware accelerator

HTML 7.47% Verilog 70.12% VHDL 0.33% SystemVerilog 16.67% Tcl 2.54% Shell 1.80% C 0.07% Python 1.00%
avalon-bus dct de1-soc embedded-systems fpga gpio-port master-slave-architecture verilog-hdl

hardware-accelerated-video-compression-using-dct's Introduction

Hardware-Accelerated-Video-Compression-using-DCT

Individual Contribution to my CPEN 391 final project. I developed the video frame capture system for the D8M, created Avalon slaves for hardware-software interfacing and the DCT hardware accelerator

Screenshot-2022-05-05-105416.png

Frame capture on the D8M system diagram:

Screenshot-2022-05-05-105446.png

Finite State Machine for the video frame retreival

Screenshot-2022-05-05-105507.png

Avalon Memory Mapped Master-Slave interface to move video frames between Hardware-Software

Screenshot-2022-05-05-105522.png

Example Signaltap instance to show signals of the FSM

Screenshot-2022-05-05-105538.png

DCT algorithm implemented in Hardware

Screenshot-2022-05-05-105554.png

DCT hardware accelerator Data flow diagram

Screenshot-2022-05-05-105606.png

Combinational logic for the 1D 8x8 DCT in hardware

Screenshot-2022-05-05-105619.png

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