This repository hosts the Cheshire SoC platform. Cheshire is a minimal Linux-capable SoC built around the RISC-V CVA6 core. It is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.

This project is still considered to be in early development; some parts may not yet be functional, and existing interfaces and conventions may be broken without prior notice. We target a formal release in the very near future.

To build different parts of the project, run make followed by these targets:

• hw-all: generated hardware, including IPs and boot ROM
• sw-all: software running on our hardware
• sim-all(†): scripts and external models for simulation
• xilinx-all: scripts for Xilinx FPGA implementation

† sim-all will download externally provided peripheral simulation models, some proprietary and with non-free license terms, from their publically accessible sources; see Makefile for details. By running sim-all or the default target all, you accept this.

Running hw-all is required at least once to correctly configure IPs we depend on. On reconfiguring any generated hardware or changing IP versions, hw-all should be rerun.

To run all build targets above (†):

make all

If you have access to our internal servers, you can run make nonfree-init to fetch additional resources we cannot make publically accessible. Note that these are not required to use anything provided in this repository.

Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see LICENSE) with the exception of generated register file code (e.g. hw/regs/*.sv), which is generated by a fork of lowRISC's regtool and licensed under Apache 2.0. All software sources are licensed under Apache 2.0.