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Add Support For Blocking
I need to enable a mix of row and column-wise accesses. Currently, all analyses must be fully row-wise or fully column-wise. This is done by blocking.
Divide by 16 in conv reference?
@David-Durst the output of each conv is divided by 16 in the conv test:
embeddedHaskellAetherling/other/conv.cpp
Line 45 in 87b7cf1
Should there be an extra stage in the conv app that does this pointwise divide or is that a leftover that can be ignored?
Resource Approximations For All Space-Time Operators
Rewrite Sequence Operators To Space-Time Operators Matching Output Type
Scheduler Parameter Scan
The auto-scheduler does a parameter search and stops when it reaches a threshold. This will implement the search.
Add Chisel Backend
Add a backend that compiles the Haskell IR to Chisel. This goal was accomplished when all 4x4 apps ran successfully in Chisel's Verilator backend.
Create Pass To Match Delays
Create a pass to match delays in the clock calculus so that all operators communicate on the same clock cycle.
Rewrite Sequence Type To Space-Time IR Type Given Slowdown
Halide to Hardware: conv2d_b2b has error: "stencil window step is not a constant" when trying to unroll accelerated loop nest
Spatial Not Going Through Synthesis
@mattfel1 thoughts? Vivado is failing for all the files. I checked a few of the logs and they said the same thing:
#-----------------------------------------------------------
# Vivado v2018.2 (64-bit)
# SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
# IP Build 2256618 on Thu Jun 14 22:10:49 MDT 2018
# Start of session at: Wed Oct 23 02:03:28 2019
# Process ID: 16086
# Current directory: /home/durst/build.2019.10.23-02.03.27
# Command line: vivado -mode batch -source system.tcl -nojournal -log vivado.log
# Log file: /home/durst/build.2019.10.23-02.03.27/vivado.log
# Journal file:
#-----------------------------------------------------------
source system.tcl
# read_verilog down_up_20.v
# read_xdc constraints.xdc
# synth_design -top top -part xc7z020clg484-1 -mode out_of_context
Command: synth_design -top top -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 16219
ERROR: [Synth 8-993] logic is an unknown type [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:50]
ERROR: [Synth 8-1031] logic is not declared [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:50]
ERROR: [Synth 8-2671] single value range is not allowed in this mode of verilog [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:53]
INFO: [Synth 8-2350] module RetimeShiftRegister ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:40]
INFO: [Synth 8-2350] module FF ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:81]
INFO: [Synth 8-2350] module SRFF ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:140]
INFO: [Synth 8-2350] module SingleCounter ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:205]
INFO: [Synth 8-2350] module RetimeWrapper ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:267]
INFO: [Synth 8-2350] module RootController_sm ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:295]
INFO: [Synth 8-2350] module SingleCounter_1 ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:505]
INFO: [Synth 8-2350] module x24_ctrchain ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:539]
INFO: [Synth 8-2350] module x35_inr_Foreach_SAMPLER_BOX_sm ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:605]
INFO: [Synth 8-2350] module RetimeWrapper_12 ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:804]
INFO: [Synth 8-2350] module x35_inr_Foreach_SAMPLER_BOX_kernelx35_inr_Foreach_SAMPLER_BOX_concrete1 ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20
.v:831]
INFO: [Synth 8-2350] module RootController_kernelRootController_concrete1 ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:907]
INFO: [Synth 8-2350] module AccelUnit ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:1051]
INFO: [Synth 8-2350] module SpatialIP ignored due to previous errors [/home/durst/build.2019.10.23-02.03.27/down_up_20.v:1469]
Failed to read verilog '/home/durst/build.2019.10.23-02.03.27/down_up_20.v'
INFO: [Common 17-83] Releasing license: Synthesis
16 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Oct 23 02:03:44 2019...
Save Test Input and Output to Separate JSON File
Previously, test input and output for the Chisel/Magma backends was included as a constant array in the source code. This doesn't scale for 1920x1080 images. I needed to save it a JSON file and load the values into the Magma/Chisel backend.
Create Clock Calculus Computations And Delay Annotations
These annotations and computations are how I'll store clock calculus information in Aetherling.
Search Space Of Space-Time Programs More Efficiently
The big_conv_2d example at 1920x1080 takes 4 minutes to compile from the sequence language to the space-time IR with a target throughput of 16 px per clock. It will not compile for the 1 px per clock version.
This is failing because the search code is slow and crashes. I need to make this more performant.
Add Support For Fold
I need to add fold in the sequence language and fold_t and fold_s in the space-time IR.
Unexpected output pattern for conv2d_b2b reference, am I missing something?
@David-Durst I'm working on big_conv2d_b2b_real. Since the input is 1920 columns by 1080 rows I was expecting the output to be of size: (1920 - 3) * (1080 - 3) = 2064609, but when I scan over the json file filtering all values that are not "253" I get: 2064605 values, four less than what I would expect.
Also I looked at the output and the 4 unexpected values are in an odd spot: 250 columns into the first valid row of output (at offsets 6012, ..., 6015 in the json output file).
Am I misunderstanding something about the output format? The first line of output seems to match up to that point.
test_json_dir not in scope
Hello,
Attempting to stack build this project throws the following error:
embeddedHaskellAetherling/src/Core/Aetherling/Interpretations/Backend_Execute/Test_Helpers.hs:232:27: error:
Variable not in scope: test_json_dir :: [Char]
|
232 | let test_file_prelude = test_json_dir ++ test_name
| ^^^^^^^^^^^^^
To finish the build I added
test_json_dir = ""
to the complaining file and the project seems to build fine. However it is not clear what is test_json_dir used for.
Create Generic Tester Interface
Previously, there were many similar functions for different types of calls to Magma for testing circuits with Verilator. This change created a uniform interface with different options. Also, that interface allows calling Verilator using circuits from Chisel or Magma.
Enable Multi-Threaded Testing
The testing bottleneck is all IO to magma. Testing would be much faster if it could be multi-threaded. I think some of this issue is because I shouldn't run multiple coreir instances simultaneously. Is that correct, Ross?
Implement More Efficient Reshape
Dillon pointed me to Memory partitioning and scheduling co-optimization in behavioral synthesis by Jason Cong for implementing reshape using HLS techniques
Separate Latency From Backend
Prior to this fix, reshape's latency was computed by calling into the Magma backend. This was slow as it required an separate IPC call for each reshape node in a space-time DAG. Now that it's computed in Haskell, this can be done much more quickly.
A second benefit of this change is the separation of the Haskell IR from the Magma backend.
Lower Clock Calculus To Magma
Create a pass to rewrite the clock calculus-annotated space-time IR to magma
Spatial Maps Not Correct
@mattfel1 I've updated the test bench so that you can pass delays as an argument:
embeddedHaskellAetherling/test/Test_Slowdown.hs
Lines 121 to 124 in 7e64186
Note that I changed the names of the files slightly. It's now map_50.v.
Are the map's correct? I'm getting the following errors for map_50.v and map_100.v:
λ: single_map_200_spatial_verilog [100/1965]
Failure with file /tmp/ae_circuit17863-830.py
Running command: ./obj_dir/Vtop
<STDOUT>
clk: 0
I: [1, 2, 3, 4, ]
O: [0, 0, 0, 0, ]
clk: 1
I: [5, 6, 7, 8, ]
O: [0, 0, 0, 5, ]
clk: 2
I: [9, 10, 11, 12, ]
O: [1, 2, 3, 9, ]
</STDOUT>
<STDERR>
Got : 0x1
Expected : 0x6
i : 70
Port : top.O[0]
</STDERR>
Found 1 error(s):
1) Got return code 1.
/home/david/anaconda3/envs/ae2/lib/python3.7/site-packages/pysmt/walkers/generic.py:43: DeprecationWarning: Using or importing the ABCs from 'collections' instead of from 'collecti
ons.abc' is deprecated, and in 3.8 it will stop working
if len(nodetypes) == 1 and isinstance(nodetypes[0], collections.Iterable):
/home/david/anaconda3/envs/ae2/lib/python3.7/site-packages/ast_tools/immutable_ast.py:10: UserWarning: /home/david/anaconda3/envs/ae2/lib/python3.7/site-packages/ast_tools/immutabl
e_ast.py generated for (3, 6)does not match system version (3, 7)
warnings.warn(f"{__file__} generated for (3, 6)"
Traceback (most recent call last):
File "/tmp/ae_circuit17863-830.py", line 90, in <module>
fault_helpers.compile_and_run_verilog(tester)
File "/home/david/dev/aetherling/aetherling/helpers/fault_helpers.py", line 124, in compile_and_run_verilog
}, directory="vBuild/", flags=["-Wno-fatal", "--trace"])
File "/home/david/dev/fault/fault/tester.py", line 302, in compile_and_run
self._compile_and_run(target=target, **kwargs)
File "/home/david/dev/fault/fault/tester.py", line 287, in _compile_and_run
self.run(target)
File "/home/david/dev/fault/fault/tester.py", line 275, in run
target_obj.run(self.actions, self.verilator_includes)
File "/home/david/dev/fault/fault/verilator_target.py", line 545, in run
disp_type=self.disp_type)
File "/home/david/dev/fault/fault/subprocess_run.py", line 142, in subprocess_run
raise AssertionError
AssertionError
Exit Code: 1
Failure with file /tmp/ae_circuit17863-834.py
Running command: ./obj_dir/Vtop
<STDOUT>
clk: 0
I: [1, 2, ]
O: [0, 5, ]
clk: 1
I: [3, 4, ]
O: [1, 7, ]
</STDOUT>
<STDERR>
Got : 0x1
Expected : 0x6
i : 35
Port : top.O[0]
</STDERR>
Found 1 error(s):
1) Got return code 1.
Installation Failed On Building ghc-tcplugins-extra on XUbuntu 18.04
ghc-tcplugins-extra > configure
ghc-tcplugins-extra > Configuring ghc-tcplugins-extra-0.3...
ghc-tcplugins-extra > build
ghc-tcplugins-extra > Preprocessing library for ghc-tcplugins-extra-0.3..
ghc-tcplugins-extra > Building library for ghc-tcplugins-extra-0.3..
ghc-tcplugins-extra > [1 of 1] Compiling GHC.TcPluginM.Extra
ghc-tcplugins-extra > [1 of 1] Compiling GHC.TcPluginM.Extra
ghc-tcplugins-extra > /usr/bin/ld.gold: error: cannot find -ltinfo
ghc-tcplugins-extra > collect2: error: ld returned 1 exit status
ghc-tcplugins-extra > `gcc' failed in phase `Linker'. (Exit code: 1)
Error:
-- While building package ghc-tcplugins-extra-0.3 using:
/home/pldi/.stack/setup-exe-cache/x86_64-linux/Cabal-simple_mPHDZzAJ_2.4.0.1_ghc-8.6.3 --builddir=.stack-work/dist/x86_64-linux/Cabal-2.4.0.1 build --ghc-options " -fdiagnostics-color=always"
Process exited with code: ExitFailure 1
Warning: Build failed, but trying to launch GHCi anyway
Configuring GHCi with the following packages: Aetherling
Warning: Didn't find expected autogen file: /home/pldi/embeddedHaskellAetherling/.stack-work/dist/x86_64-linux/Cabal-2.4.0.1/build/autogen/cabal_macros.h
Progress 1/6GHCi, version 8.6.3: http://www.haskell.org/ghc/ :? for help
<command line>: cannot satisfy -package ghc-typelits-extra-0.3
(use -v for more information)
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