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5 projects related to systemVerilog design including simple ipod, Codebreaking (Hardware Acceleration/Parallel processing) and Nios+Qsys+Direct Digital Synthesis+LFSR+Modulations+Clock Domains(+ a little bit of audio and VGA)

Verilog 11.67% SystemVerilog 3.64% Standard ML 0.01% Mathematica 0.01% VHDL 2.77% Batchfile 0.01% Coq 0.09% Makefile 0.82% Shell 0.02% Python 0.01% HTML 2.29% C 77.71% Tcl 0.03% Scala 0.31% C++ 0.17% Assembly 0.44% GDB 0.01% MATLAB 0.01%

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digital_system_design's Issues

Lab1 -- Extra Feature

  • I am thinking about adding a button to play music
  • A table for each frequency component --- this part needs to compare with wang meng

Lab1 -- Project Test_Bench

  • Get Familiar with the ModelSim test-bench
  • Create a test-bench for Clock_Divider
  • Create a test-bench for LED_Control
  • Upload the images of the result

Lab1 -- Basic Function

The basic function code including

  • use switches to control the frequency output
  • use switch [0] to turn ON and OFF the frequency output
  • Verify that the output frequency is close to the desired

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