MIT License
Copyright (c) 2023 Damien Morlier Lin Yudong Morgan Adamsson Samuel Svensson Matteo Rodriguez Derek Holzer
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This project is an open-source project adaptating the Scanimate technology used in the 80s, the goal of this project was to design an hardware accelerator that would fit on a user-affordable FPGA to meet the PAL standards at 25 frames per second with being able to control it using OSC(Open Sound Control) messages.
For this project, we have used a Pynq Z2 board and a video DAC(Texas Instruments THS 8136), you'll find the ISO file for the pynq z2 board here :
The DAC needing other components to work properly with the FPGA, we have created a kicad design than you can use to print a PCB board and don't need to figure about complex wiring.
So far the following elements have been implemented :
- Function generators with modulable parameters including different waveforms(Sawtooth, Triangle, Sinewave) and frequency, phaseshift, harmonics
- HDMI Input read
- DAC output read
- Perspective processors
- Rotation processors
- Connexion matrix to connect the function generators between then to create complex X and Y ramps
Our project is free of use and modifying and licensed under the MIT license.
This project has been created at KTH by :
- Yudong Lin
- Matteo Rodriguez
- Samuel Svensson
- Morgan Adamsson
- Damien Morlier
Under the supervision of our tutor Derek Holzer
- Pynq Z2 board :
- THS8136 :
- Boards files :
To install the project on the Pynq Z2 board :
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Set the jumper(1) to the SD side and plug in the USB powering and ethernet cable(4)(5)
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Get the ISO file of the board here :
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Flash the SD card using Rufus(https://rufus.ie/fr/) or balena etcher(https://www.balena.io/etcher)
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Insert the SD card into the SD card slot of the FPGA board(3)
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Turn on the board
If you wish to power the FPGA board using a power supply, you need to switch the jumper(2)
After a few minutes, the led DONE on the board should turn on and the ethernet connexion should be appearing
In order to send OSC messages, your computer needs to be connected to the FPGA via the ethernet cable, then you can use every OSC interface you have(or use python-osc to code in python)
Interface setup :
- IP :
- Port :
Then you can send OSC messages to the board, you can find a detailed description of the available messages at the bottom of the page
In order to edit the project, you'll need the version 2022.1 of Vivado that you can find here :
Any others versions of the tool would not be able to open the project.
Then clone the following repo :
In vivado, select Run TCL Script and then run build_ip.tcl in the repo
Then you can run the build_project.tcl script from this repo and the architecture and block design of the project should open to you
The HDMI pipeline should not be severely transformed for the integrity of the project
Our implementation of the Scanimate is located inside of the IP Datapath_DMA
After editing the project, you can then generate the bitstream and replace the board bitstream located here
And reboot the board
If you wish to modify the project and add some custom written blocks, you'll need to have knowledge in hardware description languages(VHDL, Verilog, SystemVerilog) and knowledge in digital design and expertise in using Vivado
Here is a quick tutorial on using an open-source tool to simulate your written modules in hardware description languages
sudo apt-get install ghdl
ghdl -a all-your-files
ghdl -e top-entity
ghdl -r top-entity --wave=PathToResults\Name_wave.ghw
Then you can use gtkwave to visualize your tests
./run_testbench.sh run <test-bench-entity>
Here is a list of modules that could be implemented to enhance the experience on the project
- Add an ADC input to have a external input to the connexion matrix
- Implement the HDMI output
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Detailed description of the OSC implemented : https://www.overleaf.com/read/kcfczwsqqrff
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Technical Report :