daft-freak / derp Goto Github PK

Beep.

I suspect it's possible to have support for DERP integrating directly with signal decoders/analyzers like PulseView

It looks like either TCP/IP or creating a virtual serial port to emulate the OpenBench (https://sigrok.org/wiki/Openbench_Logic_Sniffer) protocol might be the most sensible way to accomplish this. OpenBench specifically because it supports 32 channels via - I think - (an extended version of?) the SUMP protocol https://www.sump.org/projects/analyzer/protocol/.

There may be a more direct method I'm overlooking. EG: sigrok supports raw binary input data from a file, so the emulator could capture data, save on exit and let you view the traces after the fact. But it would be waaay cooler to do it in realtime.

Being able to watch registers and memory in the same way would be interesting, but would need a front-end that can understand and graph values, presumably via the GDB server. Would something like MemoryView work? https://marketplace.visualstudio.com/items?itemName=mcu-debug.memory-view

It's mostly magic numbers (with some comments). Maybe just use the hardware_regs headers from the SDK somehow?

DERP has mostly inherited the "lazy updates" from DaftBoy(Advance) with the addition of the handling of multiple clocks. This worked fine there with one "master" CPU, two peripherals that don't interact with each other and DMA that doesn't run at the same time as the CPU.

The same does not apply to the RP2040. Two CPUs that should run in parallel... and then DMA, which is itself two bus masters. Plus most of the peripherals need to sync on IO.

Currently there's enough sync for many things to work but occasionally something will get updated in the wrong order and cause an uh "time travel" problem. Another problem is the possibility for too much recursion when peripherals try to update each other. Need to come up with some plan to improve this (without syncing too much for perf reasons)... some kind of scheduling or something? 🤷

Biggest thing missing from the GDB server is being able to debug core1. (Not that multicore has been tested other than running pico3d...)

Requires handling commands like H, qC and qfThreadInfo... I think.

Seems a bit wrong for this to be missing from an RP2040 emulator.

Though I probably need to sort out DMA first.

This is all a hacky mess in MemoryBus and spams log messages (due to ignoring most registers).

It should at the very least be somewhere else.

Also, caching is unimplemented and assumes everything is cached.

Too many random printfs. Need a clearer separation between "this might not be right", "this is entirely unhandled" and actual errors.

This is a thing: https://github.com/Daft-Freak/DERP/tree/jit

Seems to work and a bit faster despite some parts being missing. Needs actual testing and maybe porting to non x86. Oh and maybe a way to turn it off for debugging.