This repository has been created as part of the "Digital Systems Design Methodologies" course at Politecnico di Milano.

The aim of the project was to synthesize different arithmetic components of approximate computing and study their power consumption.
The tools used are AUGER to generate Verilog code and Error Rate metric and OpenROAD for synthesis and report. All analysis was made on WSL2 on a Windows 10 machine.

In Review.pdf, the conclusions of the analysis can be read.

For each approximate component there is a TCL script for linking AUGER's file generation and OpenROAD systhensis. Each script needs some parameter to be pass by command line - read each file for better infos.
For AMA, AXA and InXA, where there are different versions of the same design, the design version can be specified as last command line parameter. If the parameter is ommitted, all the versions are generated and synthetized.

Parameters must be passed in the exact order
Change AUGER and OpenROAD directories in each script

• AMA: V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, "Low-Power Digital Signal Processing Using Approximate Adders”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Jan 2013.
• AXA: Z. Yang, A. Jain, J. Liang, J. Han and F. Lombardi, "Approximate XOR/XNOR-based adders for inexact computing", 2013 13th IEEE International Conference on Nanotechnology (IEEE-NANO 2013), Beijing, 2013.
• InXA: H. A. F. Almurib, T. N. Kumar and F. Lombardi, "Inexact designs for approximate low power addition by cell replacement", 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016.
• GeAr: M. Shafique, W. Ahmad, R. Hafiz and J. Henkel, "A low latency generic accuracy configurable adder", 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, CA, 2015

• DRUM: S. Hashemi, R. I. Bahar and S. Reda, "DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications", 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Austin, TX, 2015.
• RoBA: R. Zendegani, M. Kamal, M. Bahadori, A. Afzali-Kusha, and M. Pedram, “RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb 2017.

• AUGER (GitLab): Deykel Hernández-Araya, Jorge Castro-Godínez, Muhammad Shafique and Jörg Henkel, "AUGER: A Tool for Generating Approximate Arithmetic Circuits", IEEE Latin American Symposium on Circuits and Systems – LASCAS 2020, San José, Costa Rica, February 25 - 28, 2020.
• OpenROAD: https://openroad.readthedocs.io/en/latest/index.html