This repo contains the VHDL code for hardware IP for Multi-Layer Perceptron (MLP).
The VHDL code instantiates 3 modules Avalon slave, Avalon Master and NIOS soft core processor.
The Avalon master and slave are used for Direct Memory Access and parallelizing the computations.
The controller ASM and architecture datapath are detailed in the report.
The NIOS soft core processor's driver code will be updated later.