cospan / sycamore Goto Github PK

Need a Frame Buffer Platform Device/Driver to interface with a core

The device ROM table is what the interfacing MCU or CPU uses to identify the cores within the FPGA, currently there are 4 32 bit words describing each device. The 32 bit words describe the device identification number, associated flags, the memory offset from the peripheral 0x00 location and the number of registers within the core.

there should be more space for more information. Possible types of information is a pointer offset to strings, or a pointer offset to more configuration data if the 4 isn't enough.

Need a serial platform driver that will be the user side interface to a sycamore core

The UART protocol is inefficient.

right now it takes 128bits, or 16 bytes to send 4 bytes, it requires data to be sent down even when the commands for read and ping are sent down.

Here is the format
LAAAAAAABBBBBBBBCCDDDDDDEEEEEEEE

L = 'L' character
A = (24 bits) to send down (+1) including the data that is always sent down
B = (32 bits) for command, this can easily be cut down to 8bits and still leave room for growth of the command set
C = (8 bits ) device address a possible 256 devices are addressable (-2 for the DRT at 0, and the Control at 0xFF)
D = (32 bits) data

If the format were changes to
LBBAAAAACCDDDDDDEEEEEEEE
with the capability of only reading/writing certain fields when required
L = 'L' character
B = (8 bits) command
A = (20 bits) size of data (number corresponds to the number of actual bytes)
C = (8 bits) device address
D = (24 bits) address into device
E = (32 bits) data

commands can be implemented differently
Ping:
LBB

Read:
LBBAAAAACCDDDDDD

Write:
LBBAAAAACCDDDDDDEEEEEEEE(EEEEEEEE)

Response
Ping:
SBB

Read:
SBBAAAAAEEEEEEEE(EEEEEEEE)
-possibly leave out the count

Write:
SBBAAAAA

Need a GPIO platform device/driver as the user interface to a core

Need an I2C Platform Device/Driver as the user interface to a core

the project_gen.tcl script utilizes glob to search for any verilog file. When the arbitrator was added to the design it is sometimes populated when arbitrators are required, for this reason that directory can be empty. Right now glob throws an unhandled exception which crashes the script.

Need a PCIE driver to interface with Sycamore IO Handler, both sides need to be written.

There has been some success with recognizing the device with the current driver in /xylem/driver/pcie but reading and writing still need to be demonstrated as well as a protocol for transferring information between the CPU and the IO handler

Somehow a clock master must be implemented.

As it is right now certain cores will not function correctly with any clock that is different than 50MHz

Possible solutions:

-always generate a 50MHz clock with something like a digital clock manager
-find a way to 'tell' each core what the clock rate is... there must be something that defines this somewhere like a `define CLOCK_RATE or something... I could make a script that determines the clock rate from the constraints file

There are multiple cores that depend on a specific clock rate.

Need a SPI platform device that is the user interface to a core

Sycamore needs a GUI to develop projects

'parameters' within Verilog allow a for a large degree of flexibility within an already written core. 'Parameters' are core specific so as apposed to a 'define' which will be a global define for every core.

I believe that a good place in the configuration file will be within the slave braces.

What needs to be modified is the gen_top.py file, the parameters would be added when the core is instantiated. It would be good if the parameter values could verify that they are indeed within in a core instead of blindly declaring them

Need an LED platform device/driver as a user interface to a core