Options:
  -V, --version               output the version number
  -s, --asm                   generate the RISC-V assembly code instead of executing
  -r, --ir                    generate the intermediate representation (IR)
  -t, --timeout <second>      set execution timeout (in seconds)
  -o, --output <output_file>  save the output to file
  -c, --trunc                 truncate the return code to 8-bit integer
  -d, --debug                 debug mode
  -h, --help                  display help for command

Options:
  -n <step>                   run all testcases starts from step1 to this step. default is `12`.
  -s                          generate the assembly code (RISC-V) and run in the simulator instead
                              of running as an interpreter.