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antmicro hzeller umarcor alainmarcel isabella232 jeras mglb brendenpage

uhdm-integration-tests's Issues

ibex-simple-system: ibex_core.sv doesn't work in verilator

Parsing ibex_core.sv file using UHDM frontend in verilator results in Verilator internal fault, sorry, gdb bt:

Program received signal SIGSEGV, Segmentation fault.
0x0000555556088696 in vpi_handle ()
#0  0x0000555556088696 in vpi_handle ()
#1  0x0000555555bbfd10 in UhdmAst::getDType (obj_h=0x555558617920, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:264
#2  0x0000555555bc4bff in UhdmAst::visit_object (obj_h=0x555558617920, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:634
#3  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555557006d60, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#4  0x0000555555bc5a1c in UhdmAst::visit_object (obj_h=0x555557006d60, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:793
#5  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555557f06520, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#6  0x0000555555bc56e7 in UhdmAst::visit_object (obj_h=0x555557f06520, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:722
#7  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555556d55670, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#8  0x0000555555bdf453 in UhdmAst::visit_designs (designs=..., coverage_report_stream=..., symp=0x7fffffffa1b0) at ../UhdmAst.cpp:3108
#9  0x0000555555913ab8 in V3Global::readFiles (this=0x55555669f6c0 <v3Global>) at ../V3Global.cpp:140
#10 0x0000555555754b07 in verilate (argString=...) at ../Verilator.cpp:576
#11 0x00005555557561e3 in main (argc=18, argv=0x7fffffffcf88, env=0x7fffffffd020) at ../Verilator.cpp:706

Yosys uhdm frontend fails on parsing 2D arrays in module IOs

Yosys uhdm frontend fails on parsing 2D arrays in module IOs. It is creating AST node, that can't by simplified to AST_CONSTANT. It makes yosys to fail on detecting width with message:

Unsupported expression on dynamic range select on signal

Bad parameters for PLLE2_ADV in clkgen_xil7series.sv

Removing unused module ibex_multdiv_slow.sv (#48) from file list makes clkgen_xil7series.sv to pass yosys, but it fails in vivado with:

ERROR: [DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 500.000 MHz (CLKIN1_PERIOD, net io_clk_buf) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y1 (cell clkgen/pll) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (10.000000), multiplication factor CLKFBOUT_MULT_F (5) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

It is caused because PLLE2_ADV module is defined outside files, that we are parsing with Surelog and UHDM do not have information about parameters. I created separate issue for this in Surelog: https://github.com/alainmarcel/Surelog/issues/893

ibex-simple-system: ibex_simple_system.sv doesn't work in verilator

Parsing ibex_simple_system.sv file using UHDM frontend in verilator results in Verilator internal fault, sorry, gdb bt:

Program received signal SIGSEGV, Segmentation fault.
0x0000555556088696 in vpi_handle ()
#0  0x0000555556088696 in vpi_handle ()
#1  0x0000555555bbfd10 in UhdmAst::getDType (obj_h=0x5555575c48f0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:264
#2  0x0000555555bc4bff in UhdmAst::visit_object (obj_h=0x5555575c48f0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:634
#3  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555556d701e0, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#4  0x0000555555bc5a1c in UhdmAst::visit_object (obj_h=0x555556d701e0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:793
#5  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x5555583b4400, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#6  0x0000555555bc56e7 in UhdmAst::visit_object (obj_h=0x5555583b4400, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:722
#7  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555556cfc690, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#8  0x0000555555bdf453 in UhdmAst::visit_designs (designs=..., coverage_report_stream=..., symp=0x7fffffffa1b0) at ../UhdmAst.cpp:3108
#9  0x0000555555913ab8 in V3Global::readFiles (this=0x55555669f6c0 <v3Global>) at ../V3Global.cpp:140
#10 0x0000555555754b07 in verilate (argString=...) at ../Verilator.cpp:576
#11 0x00005555557561e3 in main (argc=18, argv=0x7fffffffcf88, env=0x7fffffffd020) at ../Verilator.cpp:706

Not working OneThis CI test

OneThis CI test is failing. Surelog is not generating correct UHDM. When surelog issue will be resolved, we should revisit this test. Surelog issue: alainmarcel/Surelog#938

Earlgrey: check status of every file for simulation via Surelog/UHDM -> Verilator

The purpose of this issue is to track progress in successful simulation of Earlgrey in Verilator using Surelog.
List of Earlgrey files to check:

  • top_pkg.sv
  • gpiodpi.sv
  • spidpi.sv
  • uartdpi.sv
  • usbdpi.sv
  • dv_test_status_pkg.sv
  • pins_if.sv
  • ibex_pkg.sv
  • entropy_src_pkg.sv
  • jtag_pkg.sv
  • rv_core_ibex_pkg.sv
  • usbdev_pkg.sv
  • prim_pkg.sv
  • prim_secded_22_16_dec.sv
  • prim_secded_22_16_enc.sv
  • prim_secded_28_22_dec.sv
  • prim_secded_28_22_enc.sv
  • prim_secded_39_32_dec.sv
  • prim_secded_39_32_enc.sv
  • prim_secded_72_64_dec.sv
  • prim_secded_72_64_enc.sv
  • prim_secded_hamming_22_16_dec.sv
  • prim_secded_hamming_22_16_enc.sv
  • prim_secded_hamming_39_32_dec.sv
  • prim_secded_hamming_39_32_enc.sv
  • prim_secded_hamming_72_64_dec.sv
  • prim_secded_hamming_72_64_enc.sv
  • prim_util_pkg.sv
  • top_earlgrey_pkg.sv
  • dmidpi.sv
  • jtagdpi.sv
  • sw_test_status_pkg.sv
  • sw_test_status_if.sv
  • ibex_tracer_pkg.sv
  • ibex_tracer.sv
  • lc_ctrl_state_pkg.sv
  • otbn_pkg.sv
  • prim_diff_decode.sv
  • prim_gf_mult.sv
  • tlul_pkg.sv
  • lc_ctrl_reg_pkg.sv
  • lc_ctrl_pkg.sv
  • otbn_tracer.sv
  • otbn_trace_if.sv
  • prim_generic_buf.sv
  • prim_generic_clock_buf.sv
  • prim_generic_clock_gating.sv
  • prim_generic_clock_mux2.sv
  • prim_generic_flop.sv
  • prim_generic_flop_2sync.sv
  • prim_generic_pad_wrapper.sv
  • prim_generic_ram_1p.sv
  • prim_generic_ram_2p.sv
  • prim_generic_rom.sv
  • prim_lfsr.sv
  • prim_otp_pkg.sv
  • prim_dom_and_2share.sv
  • prim_xilinx_buf.sv
  • prim_xilinx_clock_buf.sv
  • prim_xilinx_clock_gating.sv
  • prim_xilinx_clock_mux2.sv
  • prim_xilinx_flop.sv
  • prim_xilinx_pad_wrapper.sv
  • alert_handler_reg_pkg.sv
  • alert_handler_reg_top.sv
  • pwrmgr_reg_pkg.sv
  • pwrmgr_reg_top.sv
  • rstmgr_reg_pkg.sv
  • rstmgr_reg_top.sv
  • pinmux_reg_pkg.sv
  • pinmux_reg_top.sv
  • otbn_core_model.sv
  • otbn_rf_snooper_if.sv
  • otbn_stack_snooper_if.sv
  • csrng_reg_pkg.sv
  • csrng_pkg.sv
  • otp_ctrl_reg_pkg.sv
  • otp_ctrl_pkg.sv
  • otp_ctrl_part_pkg.sv
  • prim_buf.sv
  • prim_clock_buf.sv
  • prim_clock_gating.sv
  • prim_clock_mux2.sv
  • prim_flop.sv
  • prim_flop_2sync.sv
  • prim_pad_wrapper.sv
  • prim_ram_1p.sv
  • prim_ram_2p.sv
  • prim_rom.sv
  • ast_pkg.sv
  • edn_reg_pkg.sv
  • edn_pkg.sv
  • pwrmgr_pkg.sv
  • sram_ctrl_reg_pkg.sv
  • sram_ctrl_pkg.sv
  • ibex_icache.sv
  • prim_clock_gating_sync.sv
  • prim_alert_pkg.sv
  • prim_alert_receiver.sv
  • prim_alert_sender.sv
  • prim_arbiter_ppc.sv
  • prim_arbiter_tree.sv
  • prim_arbiter_fixed.sv
  • prim_esc_pkg.sv
  • prim_esc_receiver.sv
  • prim_esc_sender.sv
  • prim_sram_arbiter.sv
  • prim_fifo_async.sv
  • prim_fifo_sync.sv
  • prim_slicer.sv
  • prim_sync_reqack.sv
  • prim_sync_reqack_data.sv
  • prim_keccak.sv
  • prim_packer.sv
  • prim_packer_fifo.sv
  • prim_cipher_pkg.sv
  • prim_present.sv
  • prim_prince.sv
  • prim_subst_perm.sv
  • prim_gate_gen.sv
  • prim_pulse_sync.sv
  • prim_filter.sv
  • prim_filter_ctr.sv
  • prim_subreg_arb.sv
  • prim_subreg.sv
  • prim_subreg_ext.sv
  • prim_subreg_shadow.sv
  • prim_intr_hw.sv
  • prim_generic_clock_inv.sv
  • prim_lc_sender.sv
  • prim_lc_sync.sv
  • prim_ram_1p_adv.sv
  • prim_ram_2p_async_adv.sv
  • prim_rom_adv.sv
  • clkmgr_pkg.sv
  • flash_ctrl_reg_pkg.sv
  • flash_ctrl_pkg.sv
  • ibex_alu.sv
  • ibex_branch_predict.sv
  • ibex_compressed_decoder.sv
  • ibex_controller.sv
  • ibex_cs_registers.sv
  • ibex_csr.sv
  • ibex_counter.sv
  • ibex_decoder.sv
  • ibex_ex_block.sv
  • ibex_fetch_fifo.sv
  • ibex_id_stage.sv
  • ibex_if_stage.sv
  • ibex_load_store_unit.sv
  • ibex_multdiv_fast.sv
  • ibex_multdiv_slow.sv
  • ibex_prefetch_buffer.sv
  • ibex_pmp.sv
  • ibex_wb_stage.sv
  • ibex_dummy_instr.sv
  • ibex_register_file_ff.sv
  • ibex_register_file_fpga.sv
  • ibex_register_file_latch.sv
  • ibex_core.sv
  • flash_phy_pkg.sv
  • usb_consts_pkg.sv
  • usb_fs_nb_in_pe.sv
  • usb_fs_nb_out_pe.sv
  • usb_fs_nb_pe.sv
  • usb_fs_rx.sv
  • usb_fs_tx.sv
  • usb_fs_tx_mux.sv
  • prim_clock_inv.sv
  • prim_edn_req.sv
  • prim_generic_otp.sv
  • prim_ram_1p_scr.sv
  • prim_ram_2p_adv.sv
  • tlul_fifo_sync.sv
  • tlul_fifo_async.sv
  • tlul_assert.sv
  • tlul_err.sv
  • tlul_assert_multiple.sv
  • keymgr_pkg.sv
  • prim_otp.sv
  • flash_ctrl_reg_top.sv
  • flash_ctrl.sv
  • tlul_adapter_host.sv
  • tlul_adapter_reg.sv
  • tlul_adapter_sram.sv
  • tlul_err_resp.sv
  • tlul_socket_1n.sv
  • tlul_socket_m1.sv
  • sram2tlul.sv
  • tlul_sink.sv
  • sim_sram_if.sv
  • sim_sram.sv
  • prim_clock_div.sv
  • debug_rom.sv
  • debug_rom_one_scratch.sv
  • dm_pkg.sv
  • dm_sba.sv
  • dm_csrs.sv
  • dm_mem.sv
  • dmi_cdc.sv
  • dmi_jtag.sv
  • dmi_jtag_tap.sv
  • aes_pkg.sv
  • aes_reg_pkg.sv
  • aes_reg_top.sv
  • aes_core.sv
  • aes_ctr.sv
  • aes_control.sv
  • aes_reg_status.sv
  • aes_sel_buf_chk.sv
  • aes_cipher_core.sv
  • aes_cipher_control.sv
  • aes_sub_bytes.sv
  • aes_sbox.sv
  • aes_sbox_lut.sv
  • aes_sbox_canright_pkg.sv
  • aes_sbox_canright.sv
  • aes_sbox_canright_masked_noreuse.sv
  • aes_sbox_canright_masked.sv
  • aes_sbox_dom.sv
  • aes_shift_rows.sv
  • aes_mix_columns.sv
  • aes_mix_single_column.sv
  • aes_key_expand.sv
  • aes_prng_clearing.sv
  • aes_prng_masking.sv
  • aes.sv
  • alert_pkg.sv
  • alert_handler_reg_wrap.sv
  • alert_handler_class.sv
  • alert_handler_ping_timer.sv
  • alert_handler_esc_timer.sv
  • alert_handler_accu.sv
  • alert_handler.sv
  • edn_reg_top.sv
  • edn_ack_sm.sv
  • edn_main_sm.sv
  • edn_core.sv
  • edn.sv
  • entropy_src_reg_pkg.sv
  • entropy_src_reg_top.sv
  • entropy_src_watermark_reg.sv
  • entropy_src_cntr_reg.sv
  • entropy_src_ack_sm.sv
  • entropy_src_main_sm.sv
  • entropy_src_repcnt_ht.sv
  • entropy_src_adaptp_ht.sv
  • entropy_src_bucket_ht.sv
  • entropy_src_markov_ht.sv
  • entropy_src_core.sv
  • entropy_src.sv
  • gpio_reg_pkg.sv
  • gpio.sv
  • gpio_reg_top.sv
  • hmac_pkg.sv
  • sha2.sv
  • sha2_pad.sv
  • hmac_reg_pkg.sv
  • hmac_reg_top.sv
  • hmac_core.sv
  • hmac.sv
  • i2c_reg_pkg.sv
  • i2c_reg_top.sv
  • i2c_core.sv
  • i2c_fsm.sv
  • i2c.sv
  • keymgr_reg_pkg.sv
  • keymgr_reg_top.sv
  • keymgr_sideload_key_ctrl.sv
  • keymgr_sideload_key.sv
  • keymgr_ctrl.sv
  • keymgr_cfg_en.sv
  • keymgr_kmac_if.sv
  • keymgr_input_checks.sv
  • keymgr_reseed_ctrl.sv
  • keymgr.sv
  • nmi_gen_reg_pkg.sv
  • nmi_gen_reg_top.sv
  • nmi_gen.sv
  • otbn_controller.sv
  • otbn_decoder.sv
  • otbn_instruction_fetch.sv
  • otbn_rf_base.sv
  • otbn_rf_base_ff.sv
  • otbn_rf_bignum_ff.sv
  • otbn_rf_base_fpga.sv
  • otbn_rf_bignum_fpga.sv
  • otbn_lsu.sv
  • otbn_alu_base.sv
  • otbn_alu_bignum.sv
  • otbn_mac_bignum.sv
  • otbn_loop_controller.sv
  • otbn_stack.sv
  • otbn_core.sv
  • otbn_reg_pkg.sv
  • otbn_reg_top.sv
  • otbn.sv
  • otp_ctrl_reg_top.sv
  • otp_ctrl_ecc_reg.sv
  • otp_ctrl_scrmbl.sv
  • otp_ctrl_lfsr_timer.sv
  • otp_ctrl_part_unbuf.sv
  • otp_ctrl_part_buf.sv
  • otp_ctrl_dai.sv
  • otp_ctrl_kdi.sv
  • otp_ctrl_lci.sv
  • otp_ctrl.sv
  • pattgen_reg_pkg.sv
  • pattgen_reg_top.sv
  • pattgen_ctrl_pkg.sv
  • pattgen_core.sv
  • pattgen_chan.sv
  • pattgen.sv
  • pwrmgr.sv
  • pwrmgr_cdc.sv
  • pwrmgr_slow_fsm.sv
  • pwrmgr_fsm.sv
  • pwrmgr_wake_info.sv
  • rv_core_ibex.sv
  • rv_dm.sv
  • rv_plic_gateway.sv
  • rv_plic_target.sv
  • rv_timer_reg_pkg.sv
  • rv_timer_reg_top.sv
  • timer_core.sv
  • rv_timer.sv
  • sha3_pkg.sv
  • keccak_round.sv
  • keccak_2share.sv
  • sha3pad.sv
  • sha3.sv
  • spi_device_reg_pkg.sv
  • spi_device_reg_top.sv
  • spi_device_pkg.sv
  • spi_fwm_rxf_ctrl.sv
  • spi_fwm_txf_ctrl.sv
  • spi_fwmode.sv
  • spi_s2p.sv
  • spi_p2s.sv
  • spi_device.sv
  • sram_ctrl_reg_top.sv
  • sram_ctrl.sv
  • uart_reg_pkg.sv
  • uart_reg_top.sv
  • uart_rx.sv
  • uart_tx.sv
  • uart_core.sv
  • uart.sv
  • usbdev_reg_pkg.sv
  • usbdev_reg_top.sv
  • usbdev_usbif.sv
  • usbdev_flop_2syncpulse.sv
  • usbdev_linkstate.sv
  • usbdev_iomux.sv
  • usbdev_aon_wake.sv
  • usbdev.sv
  • prim_generic_flash_bank.sv
  • prim_generic_flash.sv
  • clkmgr_reg_pkg.sv
  • clkmgr_reg_top.sv
  • clkmgr.sv
  • sensor_ctrl_reg_pkg.sv
  • sensor_ctrl_reg_top.sv
  • tl_main_pkg.sv
  • xbar_main.sv
  • tl_peri_pkg.sv
  • xbar_peri.sv
  • csrng_reg_top.sv
  • csrng_main_sm.sv
  • csrng_state_db.sv
  • csrng_cmd_stage.sv
  • csrng_block_encrypt.sv
  • csrng_ctr_drbg_cmd.sv
  • csrng_ctr_drbg_upd.sv
  • csrng_ctr_drbg_gen.sv
  • csrng_core.sv
  • csrng.sv
  • kmac_pkg.sv
  • kmac_core.sv
  • kmac_msgfifo.sv
  • kmac_staterd.sv
  • kmac_keymgr.sv
  • kmac_entropy.sv
  • kmac_reg_pkg.sv
  • kmac_reg_top.sv
  • kmac.sv
  • lc_ctrl_reg_top.sv
  • lc_ctrl_state_decode.sv
  • lc_ctrl_state_transition.sv
  • lc_ctrl_signal_decode.sv
  • lc_ctrl_fsm.sv
  • lc_ctrl.sv
  • jtag_mux.sv
  • padring.sv
  • pinmux_pkg.sv
  • pinmux_wkup.sv
  • pinmux.sv
  • prim_flash.sv
  • rstmgr_pkg.sv
  • sensor_ctrl_pkg.sv
  • rv_plic_reg_pkg.sv
  • rv_plic_reg_top.sv
  • rv_plic.sv
  • sensor_ctrl.sv
  • flash_ctrl_erase.sv
  • flash_ctrl_prog.sv
  • flash_ctrl_rd.sv
  • flash_ctrl_arb.sv
  • flash_ctrl_info_cfg.sv
  • flash_ctrl_lcmgr.sv
  • flash_mp.sv
  • flash_mp_data_region_sel.sv
  • flash_phy.sv
  • flash_phy_core.sv
  • flash_phy_rd.sv
  • flash_phy_prog.sv
  • flash_phy_erase.sv
  • flash_phy_rd_buffers.sv
  • flash_phy_scramble.sv
  • rstmgr.sv
  • rstmgr_ctrl.sv
  • rstmgr_por.sv
  • rstmgr_crash_info.sv
  • top_earlgrey_rnd_cnst_pkg.sv
  • top_earlgrey.sv
  • top_earlgrey_verilator.sv

Ibex bitstream is not working on hardware after parsing top_artya7.sv

There is no error on parsing top_artya7.sv file by yosys, vivado is failing with:

ERROR: [Place 30-415] IO Placement failed due to overutilization. This design contains 256 I/O ports     
 while the target  device: 7a35ti package: csg324, contains only 210 available user I/O. The target device has 210 usable I/O pins of which 0 are already occupied by user-locked I/Os.
ERROR: [Place 30-68] Instance $iopadmap$ibex_core.data_rdata_i_9 (IBUF) is not placed
Placer failed with error: 'IO Clock Placer failed'

Earlgrey: check status of every file for synthesis via Surelog/UHDM -> Yosys

We need to check status of every file (Is it parsable by Surelog? Is it parsable by Yosys? Is vivado is generating bitstream? Is bitstream works on HW?). This issue is to track this progress.

  • prim_generic_clock_gating.sv
  • prim_generic_flop.sv
  • prim_generic_flop_2sync.sv
  • prim_xilinx_clock_gating.sv
  • prim_xilinx_clock_mux2.sv
  • prim_xilinx_pad_wrapper.sv
  • prim_diff_decode.sv
  • prim_generic_clock_mux2.sv
  • prim_generic_pad_wrapper.sv
  • prim_generic_ram_1p.sv
  • prim_generic_ram_2p.sv
  • prim_generic_rom.sv
  • prim_gf_mult.sv
  • prim_lfsr.sv
  • prim_clock_gating.sv
  • prim_clock_mux2.sv
  • prim_flop.sv
  • prim_flop_2sync.sv
  • prim_pad_wrapper.sv
  • prim_ram_1p.sv
  • prim_ram_2p.sv
  • prim_rom.sv
  • alert_handler_reg_top.sv
  • padctrl_reg_top.sv
  • pinmux_reg_top.sv
  • pwrmgr_reg_top.sv
  • ibex_icache.sv
  • prim_clock_gating_sync.sv
  • prim_arbiter_ppc.sv
  • prim_arbiter_tree.sv
  • prim_dom_and_2share.sv
  • prim_arbiter_fixed.sv
  • prim_esc_receiver.sv
  • prim_esc_sender.sv
  • prim_sram_arbiter.sv
  • prim_fifo_async.sv
  • prim_fifo_sync.sv
  • prim_sync_reqack.sv
  • prim_keccak.sv
  • prim_packer.sv
  • prim_present.sv
  • prim_prince.sv
  • prim_subst_perm.sv
  • prim_gate_gen.sv
  • prim_pulse_sync.sv
  • prim_filter.sv
  • prim_filter_ctr.sv
  • prim_subreg_arb.sv
  • prim_subreg.sv
  • prim_subreg_ext.sv
  • prim_subreg_shadow.sv
  • prim_intr_hw.sv
  • prim_generic_clock_inv.sv
  • prim_generic_flash.sv
  • prim_ram_1p_adv.sv
  • prim_ram_2p_async_adv.sv
  • prim_rom_adv.sv
  • ibex_alu.sv
  • ibex_controller.sv
  • ibex_cs_registers.sv
  • ibex_counter.sv
  • ibex_decoder.sv
  • ibex_ex_block.sv
  • ibex_fetch_fifo.sv
  • ibex_id_stage.sv
  • ibex_if_stage.sv
  • ibex_load_store_unit.sv
  • ibex_multdiv_fast.sv
  • ibex_multdiv_slow.sv
  • ibex_prefetch_buffer.sv
  • ibex_pmp.sv
  • ibex_wb_stage.sv
  • ibex_dummy_instr.sv
  • ibex_register_file_ff.sv
  • ibex_core.sv
  • usb_fs_nb_in_pe.sv
  • usb_fs_nb_out_pe.sv
  • usb_fs_nb_pe.sv
  • usb_fs_rx.sv
  • usb_fs_tx.sv
  • usb_fs_tx_mux.sv
  • prim_clock_inv.sv
  • prim_flash.sv
  • prim_ram_2p_adv.sv
  • tlul_fifo_sync.sv
  • tlul_fifo_async.sv
  • tlul_assert.sv
  • tlul_err.sv
  • tlul_assert_multiple.sv
  • tlul_adapter_host.sv
  • tlul_adapter_reg.sv
  • tlul_adapter_sram.sv
  • tlul_err_resp.sv
  • tlul_socket_1n.sv
  • tlul_socket_m1.sv
  • sram2tlul.sv
  • debug_rom.sv
  • debug_rom_one_scratch.sv
  • dm_sba.sv
  • dm_csrs.sv
  • dm_mem.sv
  • dmi_cdc.sv
  • dmi_jtag.sv
  • dmi_jtag_tap.sv
  • aes_reg_top.sv
  • aes_core.sv
  • aes_prng.sv
  • aes_ctr.sv
  • aes_control.sv
  • aes_reg_status.sv
  • aes_cipher_core.sv
  • aes_cipher_control.sv
  • aes_sub_bytes.sv
  • aes_sbox.sv
  • aes_sbox_lut.sv
  • aes_sbox_canright.sv
  • aes_sbox_canright_masked_noreuse.sv
  • aes_sbox_canright_masked.sv
  • aes_shift_rows.sv
  • aes_mix_columns.sv
  • aes_mix_single_column.sv
  • aes_key_expand.sv
  • aes.sv
  • alert_handler_reg_wrap.sv
  • alert_handler_class.sv
  • alert_handler_ping_timer.sv
  • alert_handler_esc_timer.sv
  • alert_handler_accu.sv
  • alert_handler.sv
  • flash_ctrl_reg_top.sv
  • flash_ctrl.sv
  • flash_erase_ctrl.sv
  • flash_prog_ctrl.sv
  • flash_rd_ctrl.sv
  • flash_mp.sv
  • flash_phy.sv
  • flash_phy_core.sv
  • flash_phy_rd.sv
  • flash_phy_prog.sv
  • flash_phy_rd_buffers.sv
  • flash_phy_scramble.sv
  • gpio.sv
  • gpio_reg_top.sv
  • sha2.sv
  • sha2_pad.sv
  • hmac_reg_top.sv
  • hmac_core.sv
  • hmac.sv
  • nmi_gen_reg_top.sv
  • nmi_gen.sv
  • otbn_reg_top.sv
  • otbn_core.sv
  • otbn.sv
  • jtag_mux.sv
  • padring.sv
  • padctrl.sv
  • pinmux_wkup.sv
  • pinmux.sv
  • rv_core_ibex.sv
  • rv_dm.sv
  • rv_plic_gateway.sv
  • rv_plic_target.sv
  • rv_timer_reg_top.sv
  • timer_core.sv
  • rv_timer.sv
  • spi_device_reg_top.sv
  • spi_fwm_rxf_ctrl.sv
  • spi_fwm_txf_ctrl.sv
  • spi_fwmode.sv
  • spi_device.sv
  • uart_reg_top.sv
  • uart_rx.sv
  • uart_tx.sv
  • uart_core.sv
  • uart.sv
  • usbdev_reg_top.sv
  • usbdev_usbif.sv
  • usbdev_flop_2syncpulse.sv
  • usbdev_linkstate.sv
  • usbdev_iomux.sv
  • usbdev.sv
  • xbar_main.sv
  • xbar_peri.sv
  • pwrmgr.sv
  • pwrmgr_cdc.sv
  • pwrmgr_slow_fsm.sv
  • pwrmgr_fsm.sv
  • pwrmgr_wake_info.sv
  • clkmgr_reg_top.sv
  • clkmgr.sv
  • rv_plic_reg_top.sv
  • rv_plic.sv
  • rstmgr_reg_top.sv
  • rstmgr_ctrl.sv
  • rstmgr_por.sv
  • rstmgr_info.sv
  • rstmgr.sv
  • top_earlgrey.sv
  • clkgen_xil7series.sv
  • top_earlgrey_nexysvideo.sv
  • ibex_pkg.sv
  • prim_alert_pkg.sv
  • ibex_compressed_decoder.sv
  • prim_secded_28_22_dec.sv
  • prim_secded_28_22_enc.sv
  • prim_secded_39_32_dec.sv
  • prim_secded_39_32_enc.sv
  • prim_secded_72_64_dec.sv
  • prim_secded_72_64_enc.sv
  • prim_alert_receiver.sv
  • prim_alert_sender.sv
  • prim_lfsr.sv
  • ibex_alu.sv
  • top_pkg.sv
  • prim_pkg.sv
  • prim_util_pkg.sv
  • flash_ctrl_pkg.sv
  • flash_phy_pkg.sv
  • tlul_pkg.sv
  • alert_handler_reg_pkg.sv
  • padctrl_reg_pkg.sv
  • pinmux_reg_pkg.sv
  • pwrmgr_reg_pkg.sv
  • prim_esc_pkg.sv
  • prim_cipher_pkg.sv
  • usb_consts_pkg.sv
  • dm_pkg.sv
  • aes_pkg.sv
  • aes_reg_pkg.sv
  • aes_sbox_canright_pkg.sv
  • alert_pkg.sv
  • flash_ctrl_reg_pkg.sv
  • gpio_reg_pkg.sv
  • hmac_pkg.sv
  • hmac_reg_pkg.sv
  • nmi_gen_reg_pkg.sv
  • otbn_pkg.sv
  • otbn_reg_pkg.sv
  • pinmux_pkg.sv
  • pwrmgr_pkg.sv
  • rv_timer_reg_pkg.sv
  • spi_device_reg_pkg.sv
  • spi_device_pkg.sv
  • uart_reg_pkg.sv
  • usbdev_reg_pkg.sv
  • tl_main_pkg.sv
  • tl_peri_pkg.sv
  • rstmgr_pkg.sv
  • clkmgr_pkg.sv
  • clkmgr_reg_pkg.sv
  • rv_plic_reg_pkg.sv
  • rstmgr_reg_pkg.sv
  • top_earlgrey_pkg.sv

Yosys is killed by OOM when parsing prim_generic_ram_1p.sv

When parsing prim_generic_ram_1p.sv yosys is killed by OOM because of using more then 32 GB of ram.
It is caused by setting mem size to Depth parameter. We need to check if Depth parameter is set correctly here and if yes, we need to verify, why yosys is using so much memory.

Verilator lacks of support for typedef input/output

EnumInPackate and StructInPackage CI tests are failing due to lack of support for input/output that is a typedef:

%Error-UNSUPPORTED: Unsupported: Member call on object 'VARREF 'var1'' which is a 'BASICDTYPE 'logic''
                            : ... In instance work_dut
%Error: Internal Error: ../V3Width.cpp:3239: How can LHS be untyped?
                                : ... In instance work_dut

%Warning-WIDTH: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh7' generates 32 or 3 bits.
                        : ... In instance work_dut
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's CONST '?32?sh38' generates 32 or 6 bits.
                        : ... In instance work_dut
%Warning-WIDTH: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's ENUMITEMREF 'SIXTH' generates 7 bits.
                        : ... In instance work_dut
%Warning-WIDTH: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's ENUMITEMREF 'SEVENTH' generates 8 bits.
                        : ... In instance work_dut
%Error: Exiting due to 4 warning(s)

Output HTML-rendered UHDM progress output to github.io as part of CI

The Surelog tests generate surelog.uhdm.chk.html files that render input files with annotations about parts that are not covered yet. This helps estimate progress and drill down particular parts.
These are generated as part of running the Surelog tests.

It would be good to have these HTML files available as part of the CI output, copied to github.io pages for easy linking (similar to how we generate the sv-tests output).

@alaindargelas is the surelog.uhdm.chk.html the only one I need to look out for ? IIRC you also had an overview list that shows the coverage percentages.

The Ibex submodule is outdated

The Ibex submodule in this repository is 5 months old.

The last commit that still works appears to be: lowRISC/ibex@8953d82

The following change breaks the build:
lowRISC/ibex@1a9545b#diff-c179907737569996eff5a53763dee97f323251b0bed22743345126b62f71d6ccR723

Errors from yosys:

1. Executing UHDM frontend.
ERROR: Encountered unhandled typespec in handle parameter: 638, node str: \MSTATUS_RST_VAL
make: *** [Makefile:13: lowrisc_ibex_top_artya7_surelog_0.1.blif] Error 1

It looks as though localparams are not properly handled here.

We need to:

  • Fix the issues with the curret ibex versions
  • Update the Ibex submodule
  • Setup cyclic submodule updates (dependabot?) to find issues in new versions automatically

Enable building of libyosys.so

Yosys has the ability to build Python wrappers for a large part of the RTLIL and it produces a libyosys.so when ENABLE_PYOSYS := 1 However, with UHDM this doesn't work because it is making a static library. Is there a way to also build a .so so that a libyosys.so can be built? Here is the relevant error msg:

[100%] Building yosys
[100%] Building libyosys.so
/usr/bin/ld: ./../image/lib/uhdm/libkj.a(exception.c++.o): relocation R_X86_64_TPOFF32 against `_ZN2kj12_GLOBAL__N_1L19threadLocalCallbackE' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: ./../image/lib/uhdm/libuhdm.a(clone_tree.cpp.o): relocation R_X86_64_PC32 against symbol `_ZTVN4UHDM9attributeE' can not be used when making a shared object; recompile with -fPIC
/usr/bin/ld: final link failed: bad value
clang: error: linker command failed with exit code 1 (use -v to see invocation)
make[1]: *** [Makefile:678: libyosys.so] Error 1
make[1]: *** Waiting for unfinished jobs....
make[1]: Leaving directory '/home/macd/oroad/code/uhdm-integration/yosys'
make: *** [Makefile:32: yosys/yosys] Error 2

Moving GH actions from uhdm-integration to verilator and yosys.

The purpose of this issue is to monitor and get everything right while moving GH actions from uhdm-integration to verilator and yosys (in Antmicro forks). The following PRs need to be merged (in this order):

Remember to update name of submodules branches after every merge, because they are pointing now to WiP branches.

/cc @tgorochowik

ibex-simple-system: bus.sv doesn't work in verilator

Parsing bus.sv file using UHDM frontend in verilator results in:

%Warning-WIDTH: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's SEL generates 2 bits.                                                                                                  [1/45665]
                        : ... In instance ibex_simple_system.u_bus                                                                                                                                                 
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Warning-WIDTH: Operator EQ expects 2 bits on the RHS, but RHS's VARREF 'device_sel_req' generates 1 bits.
                        : ... In instance ibex_simple_system.u_bus
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:161:6: Slices of arrays in assignments have different unpacked dimensions, 1 versus 3
                                                                                : ... In instance ibex_simple_system.cfg_device_addr_mask
  161 |     .cfg_device_addr_mask
      |      ^~~~~~~~~~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:160:6: Slices of arrays in assignments have different unpacked dimensions, 1 versus 3
                                                                                : ... In instance ibex_simple_system.cfg_device_addr_base
  160 |     .cfg_device_addr_base,
      |      ^~~~~~~~~~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:158:27: Slices of arrays in assignments have different unpacked dimensions, 1 versus 3
                                                                                 : ... In instance ibex_simple_system.device_err
  158 |     .device_err_i        (device_err   ),
      |                           ^~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:157:27: Slices of arrays in assignments have different unpacked dimensions, 1 versus 3
                                                                                 : ... In instance ibex_simple_system.device_rdata
  157 |     .device_rdata_i      (device_rdata ),
      |                           ^~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:156:27: Slices of arrays in assignments have different unpacked dimensions, 1 versus 3
                                                                                 : ... In instance ibex_simple_system.device_rvalid
  156 |     .device_rvalid_i     (device_rvalid),
      |                           ^~~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:155:6: Slices of arrays in assignments have different unpacked dimensions, 3 versus 1
                                                                                : ... In instance ibex_simple_system.__Vcellout__u_bus__device_wdata_o
  155 |     .device_wdata_o      (device_wdata ),
      |      ^~~~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:154:6: Slices of arrays in assignments have different unpacked dimensions, 3 versus 1
                                                                                : ... In instance ibex_simple_system.__Vcellout__u_bus__device_be_o
  154 |     .device_be_o         (device_be    ),
      |      ^~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:153:6: Slices of arrays in assignments have different unpacked dimensions, 3 versus 1
                                                                                : ... In instance ibex_simple_system.__Vcellout__u_bus__device_we_o
  153 |     .device_we_o         (device_we    ),
      |      ^~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:152:6: Slices of arrays in assignments have different unpacked dimensions, 3 versus 1
                                                                                : ... In instance ibex_simple_system.__Vcellout__u_bus__device_addr_o
  152 |     .device_addr_o       (device_addr  ),
      |      ^~~~~~~~~~~~~
%Error: ../src/lowrisc_ibex_ibex_simple_system_0/rtl/ibex_simple_system.sv:151:6: Slices of arrays in assignments have different unpacked dimensions, 3 versus 1
                                                                                : ... In instance ibex_simple_system.__Vcellout__u_bus__device_req_o
  151 |     .device_req_o        (device_req   ),
      |      ^~~~~~~~~~~~
%Warning-COMBDLY: Delayed assignments (<=) in non-clocked (non flop or latch) block
                  ... Suggest blocking assignments (=)
                  *** See the manual before disabling this,
                  else you may end up with different sim results.
%Error: Exiting due to 10 error(s), 3 warning(s)

Yosys regressions with Surelog 241bf56

There are some problems in Yosys that appeared with the newest Surelog:

  • missing handling of typespec 618 (vpiStructVar),
  • a segfault in the cleanup procedure after parsing Ibex,
  • a segfault after parsing Ibex and passing the AST on to simplify,
  • tests IndexedPartSelect, PartSelect, VarSelect are failing.

I suspect at least a few of these share their root cause.

ibex_simple_system: ram_2p.sv doesn't work in verilator

Parsing ram_2p.sv (with prim_generic_ram_2p.sv and prim_ram_2p.sv) file using UHDM frontend in verilator results in:

%Error-UNSUPPORTED: Unsupported: Slice of non-constant bounds
                            : ... In instance ibex_simple_system.u_ram.u_ram..u_impl_generic
%Error: Internal Error: ../V3Width.cpp:1015: AstSelPlus should disappear after widthSel
                                : ... In instance ibex_simple_system.u_ram.u_ram..u_impl_generic
                        ... See the manual and https://verilator.org for more assistance.

ibex-simple-system: ibex_core_tracing.sv doesn't work in verilator

Parsing ibex_core_tracing.sv file using UHDM frontend in verilator results in Verilator internal fault, sorry, gdb bt:

Program received signal SIGSEGV, Segmentation fault.
0x0000555556088696 in vpi_handle ()
#0  0x0000555556088696 in vpi_handle ()
#1  0x0000555555bbfd10 in UhdmAst::getDType (obj_h=0x555556e1e6a0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:264
#2  0x0000555555bc4bff in UhdmAst::visit_object (obj_h=0x555556e1e6a0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:634
#3  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x5555582fe8b0, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#4  0x0000555555bc5a1c in UhdmAst::visit_object (obj_h=0x5555582fe8b0, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:793
#5  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x55555812a920, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#6  0x0000555555bc56e7 in UhdmAst::visit_object (obj_h=0x55555812a920, visited=..., top_nodes=0x7fffffff9f60) at ../UhdmAst.cpp:722
#7  0x0000555555bbdfa9 in UhdmAst::visit_one_to_many(std::vector<int, std::allocator<int> >, unsigned int*, std::set<UHDM::BaseClass const*, std::less<UHDM::BaseClass const*>, std::allocator<UHDM::BaseClass const*> >, std::map<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, AstNodeModule*, std::less<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > >, std::allocator<std::pair<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > const, AstNodeModule*> > >*, std::function<void (AstNode*)> const&) (childrenNodeTypes=..., parentHandle=0x555556d02f80, visited=..., top_nodes=0x7fffffff9f60, f=...) at ../UhdmAst.cpp:32
#8  0x0000555555bdf453 in UhdmAst::visit_designs (designs=..., coverage_report_stream=..., symp=0x7fffffffa1b0) at ../UhdmAst.cpp:3108
#9  0x0000555555913ab8 in V3Global::readFiles (this=0x55555669f6c0 <v3Global>) at ../V3Global.cpp:140
#10 0x0000555555754b07 in verilate (argString=...) at ../Verilator.cpp:576
#11 0x00005555557561e3 in main (argc=18, argv=0x7fffffffcf88, env=0x7fffffffd020) at ../Verilator.cpp:706

Your .dependabot/config.yaml contained invalid details

Dependabot encountered the following error when parsing your .dependabot/config.yaml:

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ibex-simple-system: ibex_register_file_latch.sv doesn't work in verilator

Parsing ibex_register_file_latch.sv file using UHDM frontend in verilator results in %Error: Exiting due to 1 error(s) (without any more message), running with --debug flag says:

%Error: Exiting due to 1 error(s)                                                                        
- V3Ast.cpp:1120:     Dumping ./Vibex_simple_system_990_final.tree                                                                                                                                                 
%Error: Internal Error: ../V3Broken.cpp:253: Broken link in node->dtypep() to 0x5555578f12f0
-node: VAR (AEEB) <e51363> {d0aa} @dt=(BEEB)@(nw1)  file INPUT PORT
%Error: Internal Error: Aborting since under --debug

ibex-simple-system: ibex_cs_registers.sv doesn't work in verilator

Parsing ibex_cs_registers.sv with ibex_csr.sv and ibex_counter.sv (ibex_cs_registers.sv is using them, so they need to be parsed together) file using UHDM frontend in verilator results in:

%Error: Duplicate declaration of TYPEDEF 'status_t': 'status_t'
        ... Location of original declaration
%Error: Duplicate declaration of enum value: PRIV_LVL_H
        ... Location of original declaration
%Error: Duplicate declaration of enum value: PRIV_LVL_M
        ... Location of original declaration
%Error: Duplicate declaration of enum value: PRIV_LVL_S
        ... Location of original declaration
%Error: Duplicate declaration of enum value: PRIV_LVL_U
        ... Location of original declaration
%Error: Duplicate declaration of TYPEDEF 'dcsr_t': 'dcsr_t'
        ... Location of original declaration
%Error: Duplicate declaration of TYPEDEF 'status_stk_t': 'status_stk_t'
        ... Location of original declaration
%Warning-IMPLICIT: Signal definition not found, creating implicitly: 'rd_error_o'
                   ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message.
%Error: Exiting due to 7 error(s), 1 warning(s)

Yosys frontend sometimes wrongly parses parameters

Assignment-patterns AST differs when used in parameters parameters (there is no AST_ASSIGN when assigning to parameter). Currently yosys frontend fails on parsing this type of parameters and creates parameter without any children. This ends up with segmentation fault.

Yosys uhdm frontend is creating modules on usage

Yosys uhdm frontend doesn't distinguish usage of module from a definition and it is always creating module if it can't find one. Example:

image/bin/surelog -parse -sverilog tests/ibex/ibex/build/lowrisc_ibex_top_artya7_0.1/src/lowrisc_ibex_fpga_xilinx_shared_0/rtl/fpga/xilinx/clkgen_xil7series.sv
yosys/yosys -p "read_uhdm -debug slpp_all/surelog.uhdm"

UHDM Output:

    |vpiModule:
    \_module: work@clkgen_xil7series::BUFG (work@clkgen_xil7series.clk_fb_bufg) clkgen_xil7series.sv:63     : , parent:work@clkgen_xil7series
      |vpiDefName:work@clkgen_xil7series::BUFG
      |vpiName:clk_fb_bufg
      |vpiFullName:work@clkgen_xil7series.clk_fb_bufg
      |vpiPort:
      \_port: (I), parent:work@clkgen_xil7series.clk_fb_bufg
        |vpiName:I
        |vpiHighConn:
        \_ref_obj: (clk_fb_unbuf), line:64
          |vpiName:clk_fb_unbuf
          |vpiActual:
          \_logic_net: (@@BAD_SYMBOL@@), line:16, parent:work@clkgen_xil7series
      |vpiPort:
      \_port: (O), parent:work@clkgen_xil7series.clk_fb_bufg
        |vpiName:O
        |vpiHighConn:
        \_ref_obj: (clk_fb_buf), line:65
          |vpiName:clk_fb_buf
          |vpiActual:
          \_logic_net: (@@BAD_SYMBOL@@), line:15, parent:work@clkgen_xil7series

Yosys AST output:

    AST_MODULE <slpp_all/surelog.uhdm:0.0-0.0> [0x5574caf67130] str='\clkgen_xil7series::BUFG' basic_prep
       AST_WIRE <slpp_all/surelog.uhdm:0.0-0.0> [0x5574caf67f60] str='\I' basic_prep port=30 range=[0:0]
       AST_WIRE <slpp_all/surelog.uhdm:0.0-0.0> [0x5574caf680a0] str='\O' basic_prep port=31 range=[0:0]

clkgen_xil7series::BUFG module was created, but it was just used in clkgen_xil7series.sv.

UHDM-Verilator: Regression in VarSelect test

VarSelect test fails with:

%Error: Extracting 32 bits from only 8 bit number
                : ... In instance work_top
%Warning-WIDTH: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's SEL generates 32 bits.
                        : ... In instance work_top
                ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 error(s), 1 warning(s)

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