cfelton / minnesota Goto Github PK

Current usage:

# memory-mapped registers
greg = regfile.m_per_interface(clock, reset, regbus,
                                           base_address=base_address)
regbus.add('led', regfile, base_address)

Change to

# memory-mapped registers
greg = regbus.add('led', regfile, base_address)

The RegisterFile process should be:

regfile = RegisterFile(**params)
reg = Register(**params)
regfile.add_register(reg)

Instead of creating the OrderedDict and constructing.

Currently the memory-map register bus (CSR) follows the old-school scheme defining the data and address bus widths. This shouldn't be the case. Once the bus is defined it should decide the address space and data widths. High-level parameters can be provided to help steer the building, example max throughput and addressing type (one-hot, etc.).

The builder will then output a map and structures to automatically access.