cambridgehackers / fpgamake Goto Github PK

This is what I did and what I get for errors so far:

1.) Downloaded a tutorial. (would be great if there was package in the fpgamake repo, or perhaps you could use the Parallella project once ready?)

https://secure.xilinx.com/webreg/clickthrough.do?cid=363329&cancellink=http%3A%2F%2Fwww.xilinx.com%2Fsupport%2Fdocumentation%2Findex.htm

2.) ./fpgamake --board='noboard' --part='xc7k70tfbg676-2' -b top.bit -o fpgamake.mk -t sys_integration_top --constraints=/home/aolofsson/Work_others/fpgamake/ug939-design-files/lab_4/sources/Constraints/top.xdc /home/aolofsson/Work_others/fpgamake/ug939-design-files/lab_4/sources/HDL

3.) make -f fpgamake.mk
parallella:~/Work_others/fpgamake> make -f fpgamake.mk
fpgamake.mk Synth/sys_integration_top/sys_integration_top-synth.dcp
/bin/sh: /home/aolofsson/Work_others/buildcache/buildcache: No such file or directory
make: *** [Synth/sys_integration_top/sys_integration_top-synth.dcp] Error 127

4.) realized that I had to clone your 'buildcache' repo parallel to the fpgamake? Did I miss this in the help?

5.) Working my way through example now....

I put in the wrong argument for "-t" so the file top.v didn't exist. That gave me the following message. Would be nice if flow gave a clearer hint as to the where the error might be (for idiots like me:-))

File "./fpgamake", line 498, in
process_modules()
File "./fpgamake", line 227, in process_modules
shutil.copyfile(vpath, os.path.join(synthdir, vfile))
File "/usr/lib/python2.7/shutil.py", line 68, in copyfile
if _samefile(src, dst):
File "/usr/lib/python2.7/shutil.py", line 58, in _samefile
return os.path.samefile(src, dst)
File "/usr/lib/python2.7/posixpath.py", line 162, in samefile
s1 = os.stat(f1)
TypeError: coercing to Unicode: need string or buffer, NoneType found

I'm running Mint Linux 19.2, and I used the apt get method to install the fpgamake software on my machine.
One of the first steps I am trying is to build an example project, but I'm not able to, it seems like the 'bsc' command is missing on my machine?
The documentation doesn't mention anything about bsc.
Please let me know if more information is needed.

Output from: make

/usr/bin/time bsc -u -verilog -elab -reset-prefix RST_P -D BSV_POSITIVE_RESET \
-p +:bsv \
-bdir /home/paul/work/fpga/fpgamake/fpgamake/examples/uart_kc705/kc705/bo -vdir verilog -info-dir /home/paul/work/fpga/fpgamake/fpgamake/examples/uart_kc705/kc705/info -p :+ -no-show-method-conf \
-show-schedule -show-compiles -aggressive-conditions -keep-fires -no-inline-rwire   \
-remove-dollar -show-range-conflict -scheduler-effort 500 bsv/DutTop.bsv
/usr/bin/time: cannot run bsc: No such file or directory
Command exited with non-zero status 127
0.00user 0.00system 0:00.00elapsed ?%CPU (0avgtext+0avgdata 1120maxresident)k
0inputs+0outputs (0major+27minor)pagefaults 0swaps
Makefile:17: recipe for target 'verilog/mkDutTop.v' failed
make: *** [verilog/mkDutTop.v] Error 127

One thing that would help me (and possibly others) get up to spee quickly would be if I could use the same source command file that I use for icarus and verilator (arguably the two most popular open source simulators) to feed the fpgamake tool. The argument would typically be "-f my.cmd".

During evaluation, either read the file list as specified in command file or read the constants first. (the constants parts has given me problems in chip and synthesis tools).

An example of the content of the command file can be seen here.

../../constants/hdl/simulation_constants.v
../../elink/hdl/elink_regmap.v
dv_elink_tb.v
-y .
-y ../../elink/hdl
-y ../../stubs/hdl
-y ../../common/hdl
-y ../../memory/hdl
-y ../../embox/hdl
-y ../../emmu/hdl

The argument list doesn't match output of ./fpgamake -h
(for example --xdc seems to have been replaced by --constraints)

hi,
how do I install the bsv compiler?

thanks