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I'm trying to run the Connectal echo example on the VCU118; this error message pops up and the process dies without success.

fpgajtag: Digilent:Digilent USB Device:210308AE6FD7; bcd:900
[init_fpgajtag] id 20000000 from file does not match actual id 4b31093
subprocess pid 26834 completed status=ff00 255

Our FPGA board is connected via JTAG to the host machine running Ubuntu 18.04. The JTAG+Connectal drivers seem to be correctly installed (board shows up in the Vivado Hardware Manager). Is there any reason this message would appear?

Sorry for asking the easy question，But I can't run this program. When i use this command ，it just stoped . I don't know if there is something wrong with my usage。 Following is my command. I hope you can put a expample for using this programe. Thank you for your help！

sudo ./fpgajtag -a -l ttyUSB0 no_header_Single_Lut.bit
fpgajtag: Digilent:Digilent USB Device:210251A08870; bcd:900

Could you add some documentation of the command line options?

I'm trying to adapt fpgajtag to do simple boundary scans on Xilinx FPGAs, since there seems to be no good alternatives: Vivado seems to lack a simple means of connecting to an FPGA and extracting the boundary scan (or is so complicated, that I can't find out how to do it) and seems to hang on some connections, and OpenOCD seems to be able to do just about everything with JTAG, except for simple boundary scans. fpgajtag, in contrast, is beautifully simple, and never hangs the way Vivado does for me. My only challenge is to understand the code enough to be able to adapt it to my purposes.

I've been looking at read_idcode() as what should be a simple JTAG transaction that is in many ways similar to doing a boundary scan. However, I can't for the life of me figure out how it actually works to send the JTAG command. My understanding is that the JTAG command for IDCODE is 001001, but I see nothing suggestive of this in read_idcode().

What I would love, is to be able to craft something like the following (taken from https://www.fpga4fun.com/JTAG4.html) to be able to easily build JTAG transactions in the fpgajtag code base:

// go to reset state
  for(i=0; i<5; i++) JTAG_clock(TMS);

  // go to Shift-IR
  JTAG_clock(0);
  JTAG_clock(TMS);
  JTAG_clock(TMS);
  JTAG_clock(0);
  JTAG_clock(0);

  // Assuming that IR is 10 bits long,
  // that there is only one device in the chain,
  // and that SAMPLE code = 0000000101b
  JTAG_clock(1);
  JTAG_clock(0);
  JTAG_clock(1);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0);
  JTAG_clock(0 or TMS);  // last bit needs to have TMS active, to exit shift-IR

  // we are in Exit1-IR, go to Shift-DR
  JTAG_clock(TMS);
  JTAG_clock(TMS);
  JTAG_clock(0);
  JTAG_clock(0);

  // read the boundary-scan chain bits in an array called BSB
  JTAG_read(BSB, 339);
  printf("Status of pin 99 = %d\n, BSB[3]);

Any pointers for how I would go about constructing such a sequence using the fpgajtag infrastructure?

Thanks,
Paul.

Hello again, your chief causer of issues,

We have been porting fpgajtag to Windows (or rather, the version embedded into our MEGA65 debug tool).

We have managed to produce a binary that runs, can talk to the FTDI serial and JTAG interfaces, and can even do the JTAG device detection. However, when it comes to actually transferring a bitstream (which of course is our goal), it has trouble:

We get results like this:

X:\monitorload>monitor_load8.exe -l COM11 -b mega65r2test.bit
Getting started..
#0: fpgajtag: Digilent:Digilent USB Device:251633059648; bcd:700
Trying usb_index=0
USB device info: dev=000000001A7DAA60, idVendor=403, idProduct=6010, bcdDevice=700(0d1792)
USB bus=2, port_number=3
I'm on windows, and don't (yet) know how to work out the COMx: path.
In case it helps: bus=2, port=3
count 0/1 cortex -1 dcount 0 trail 0
STATUS 00401079 done 0 release_done 0 eos 10 startup_state 0
fpgajtag: Starting to send file
fpgajtag: Done sending file
[fpgajtag_main:1020] CONFIG_REG_BOOTSTS mismatch 0
[fpgajtag_main:1024] mismatch 88
fpgajtag: bypass first time 20
STATUS 00700019 done 0 release_done 0 eos 10 startup_state 4
fpgajtag: ERROR failed to run pciescanportal: No such file or directory
[T+3sec] Bitstream loaded

The FPGA board gets de-configured, but never completes the configuration process -- presumably because something (hopefully simple) has gone wrong in the setup prior to that point. We realise that this is not totally core for yourselves, but if in your USB hacking experience are able to offer any ideas on what might be going, this would be super helpful?

We have tried to do a bit of USB traffic capture using wireshark, but are happy to admit that we are clueless when it comes to understanding USB traffic.

The only things I have been able to see so far, is that Windows sends many smaller frames during the setup stage, compared with on Linux. Under Windows the bulk transfer of the bitstream then seems to die after sending just three packets.

Is it maybe some buffer getting full, perhaps

I have attached the two traces here, if they help provide any clues.

linux-working.pcap.gz
windows-notworking.pcap.gz

Thanks for any light you can help us shine on this,
Paul

Hello again, your favourite issue submitter here ;)

We were wondering how feasible it would be to add support for pushing bitstreams to Intel MAX10 FPGAs to fpgajtag?
(Basically Quartus the official tool is a bit of a tool, in that it doesn't support all JTAG adapters, which rather inconveniences us).

Thanks,
Paul.

Hello again,

Now I am trying to extend fpgajtag so that it works with a new FPGA board I bought, that seems to have a different pinout on the FTDI side of things, the Mimas A7.

First step, the device uses a different vendor and product id, which was easy enough to patch in util.c with something like:

        if (
	    // FTDI-based boards from Trenz, Digilent etc
	    ( desc.idVendor == 0x403 && (desc.idProduct == 0x6001 || desc.idProduct == 0x6010
					 || desc.idProduct == 0x6011 || desc.idProduct == 0x6014))
	    ||
	    // Mimas A7 and similar boards
	    ( desc.idVendor == 0x2a19 && (desc.idProduct == 0x1009 ))
	    )
	  { /* Xilinx */

With that in place, I can find the USB device, but thte JTAG boundary scan indicates IDs of all zero. This is caused by the funny FTDI JTAG pinout they are using, as far as I can tell.
Fortunately, there is an OpenOCD config file that explains the setup required for that:

https://numato.com/kb/programming-mimas-a7-using-openocd-and-xc3sprog/

And this page from Numato has the FTDI pinouts:

https://numato.com/docs/mimas-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet/

My guess is that we need to rearrange the bits in the bytes when read/written to the FTDI.

Mimas A7 schematic from https://numato.com/docs/mimas-artix-7-fpga-development-board-with-ddr-sdram-and-gigabit-ethernet/ indicates that the JTAG pins on the FTDI are:

BDBUS0 = TCK
BDBUS1 = TDI
BDBUS2 = TDO
BDBUS3 = TMS

While on the TE0790 JTAG programming adapter that does work with fpgajtag, they are on:

ADBUS0 = TCK
ADBUS1 = TDI
ADBUS2 = TDO
ADBUS3 = TMS

So we don't need to fiddle bits -- just change the FTDI commands to work on the BDBUS instead of the ADBUS.... however that works. Currently trying to figure that part out...

Is there any documentation for your .jtag file format?