DE2-vd is a video digitization add-on module for Altera DE2-115 FPGA development board. Together with DE2-115, it can be used in converting analog RGB/component video into digital format with very low processing latency. The system is mainly designed for using retro game consoles / home computers on modern displays.

The module is a prototype for a single-board digitization and scan converter system to be released in the future. Therefore, the current system is targeted for developers / hobbyists interested in FPGA design and video digitization - no in-depth documentation is currently provided.

• detects and digitizes various video modes from 240p to 1280x1024 (and possibly higher with future updates)
• linedouble-support for 240p, 480i, 288p, 576i
• linetriple-support for 240p with 4 different sampling modes
• very low latency (less than 2 input scanlines)
• single-field "deinterlace" for 480i/576i: minimal latency overhead with decent image quality
• quick recover from input video mode change (e.g. 240p<->480i)
• all video processing done in RGB domain - no conversion to YCbCr
• multiple inputs supporting various formats
• RGBS via SCART connector
• RGBHV/RGBS via VGA connector
• YPbPr/RGsB via 3xRCA connector
• Two possible output methods
• full-range RGB output through HDMI
• analog RGB output through VGA DAC
• emulated scanlines with configurable strength
• configurable mask for overscan area
• configurable horizontal sample rate (only limited by display support)
• fully open source: rtl, software and pcb design files all avaiable for modification

• Hardware

• Altera DE2-115 FPGA development board

• HDMI Transmitter Daughter Card (optional, for HDMI output)

• DE2-vd PCB and components

• SMA and 2x20 ribbon cables between the boards (as short as possible)

• 5V DC power supply (min. 1A, 1.3/4.5mm center positive)

• Software

• Altera Quartus II (v 14.1 or higher - free Web edition available)

• Altera University Program IP (for on-board LCD character display)

DE2-vd module connections

DE2-115 board controls and connections

1. Edit rtl/output_sel.v.example to suit your setup, and save the modified file into rtl/output_sel.v
2. Load the project (videoproc.qpf) in Quartus II
3. Generate Qsys system files (Tools -> Qsys. Open sys.qsys -> Generate -> Generate HDL)
4. Generate the FPGA bitstream (Quartus window -> Processing -> Start Compilation)
5. Program the bitstream into the FPGA using either JTAG (volatile/.sof) or AS programming (nonvolatile/.pof) method

Before turning on the power, set jumpers JP7 and JP8 on the DE2-115 development board into 3.3V position. After programming the FPGA, the character LCD and 7-segment LEDs should display "OSSC" if the connection between the boards is operational.

Active input and format can be selected by using the 3 leftmost push-buttons on the board (see connection diagram). The inputs and corresponding connectors and formats are listed in the following table. The format within one input can be switched by pressing the same input button again.

With SD video input, the line multiplier is activated in order to generate an output which is accepted by the target display. By default, the system uses linedouble and a horizontal sampling rate which results to 720 active pixels (720x480 with 60Hz, 720x576 with 50Hz). This is a standard mode which is compatible with basically all HDMI-enabled displays.

With 240p input, it is possible to improve output quality by enabling linetripler (L3_ENABLE=1) and selecting a suitable sampling mode (L3_MODE). This allows sampling the input video with a rate which matches the rate of the DAC generating the video, or alternatively with significant oversampling. Moreover, the output resolution (1280x720) is closer to the native resolution of modern displays, resulting to less scaling. There features reduce the softness resulting from inoptimal sampling and/or scaling. The sampling modes are as follows:

NOTE: the 1280x720 mode outputted by linetripler does not match the standardized 1280x720 mode and is not guarateed to work correctly on all displays.

Emulated scanlines can be enabled with SCANLINES_ENABLE-switch, and their strength is adjusted by SCANLINE_STR[2:0]. Scanlines are active every other output line with linedouble/bare digitize, and every third output line with linetriple.

Up to 15 pixels of input video's borders can be masked with black bars in horizontal and vertical direction via H_MASK[3:0] and V_MASK[3:0] switches.